DAC5681Z: The self test mode give me error, where and how can I find more detail about where is the error come from?

Here are the registers readback after I do the self test
0x0 0x0b
0x1 0x18
0x2 0xea
0x3 0xb0
0x4 0x40 This is the self test fault? What can I do?
0x5 0x06
0x6 0x0f
0x7 0xff
0x8 0x00
0x9 0x00
0xa 0x00
0xb 0x00
0xc 0x0a
0xd 0x55
0xe 0x0a
0xf 0xaa

If I don't do the self test, just initialize the chip, I can read back as below
0x0 0xcb # this showing I have PLL and DLL working. For me, that is telling me the clock is connected correctly
0x1 0x01 # I am not using FIR filter, maybe I should? I do see lot of glitching, and trying to figure out if that come from my FPGA or not?
0x2 0xc0
0x3 0x00 # Do not mask anything.
0x4 0x30 # I do get fifo err and pattern err, why? how can I tell?
0x5 0x40
0x6 0x0c
0x7 0xff
0x8 0x00
0x9 0x00
0xa 0xb0
0xb 0x00
0xc 0x00
0xd 0x00
0xe 0x00
0xf 0x00

Can you please describe your issue in more detail. I am not able to fully understand your issue.
I have a FMC110 board from 4dsp, which as two DAC5781z. (www.ti.com/.../thirdpartydevtoolfolder.tsp
I am trying to write FPGA code for it.
Can you please explain your setup(CLK rate, data rate, mode of operation etc).
CLK at 1000MHz, data at 500MHz DDR. Inside the FPGA, using 125MHz and 1:8 serdes generating the data.

Have you tried a different board and are you seeing the same issue on the other boards?
No, I have but only this board.
Also when you mention chip is kind of working, Can you please elaborate on what is happing when the chip is not working?
The chip does output waveform almost as what I programmed, except has lots of glitch in time domain.
In order to debug the glitching, I think it would be good to check the self test mode, but I got failure. And also in normal operation, I got FIFO err and Pattern err.

Thanks,
Gang

It seems I can clear the pattern err by send 0xaaaa to the DAC, but I can not clear the FIFO err.