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DAC39J84: The setup time between the device clock and SYSREF

Zhipeng lv
Intellectual 465 points
Part Number: DAC39J84
Other Parts Discussed in Thread: LMK04828,

Hi deer TI

 

I use LMK04828 to supply device clock and SYSREF to DAC39J84 on my own board. There are  some questions about the setup time between  device clock and SYSREF.

 

1.My JESD204B configuration is LMF = 841 HD =1 k =32. My device clock = 600MHz, SYSREF = 9.375MHz. The frequency of device clock is much higher than SYSREF. There is no doubt that SYSREF will be sampled by device clock. In other words even though the first rise edge of device clock doesn't sample the SYSREF ' high level. There must be a rise edge of device clock can sample the SYSREF ' high level after the first one. Is it necessary to set the setup time between Device clock and SYSREF.(As the data sheet of DAC39J84 setup time =50ps) 

2.Whether DAC39J84 just only recognize the first rise edge of device clock to sample the SYSREF? If the first rise edge of device clock doesn't meet the setup time requirement whether the next rise edge that can sample the sysref also can not be recognized by DAC39J84.

Regards

Zhipeng

 

  • 0
    TI__Guru* 91947 points

    Zhipeng,

    If you do not need the DAC to have a deterministic latency, this is not an issue. If you require the latency to be deterministic, the SYSREF must meet the setup and hold of device clock. If you leave SYSREF running, the setup and hold time must be meet for every cycle of SYSREF. You cannot sample SYSREF one clock cycle early then one clock cycle late as this will throw off the timing of the internal clocks.

    Regards,

    Jim 

  • 0 in reply to jim s
    Intellectual 465 points
    Jim

    According to your description the deterministic latency is not a necessary condition. If I just send a 9.375MHz SYSREF synchronizing with 600MHz device clock regardless of the setup time. Does it have influence on the usage on DAC39J84? If SYSREF can not be sampled on the first rise edge of device clock. Can it be sampled on the second or third rise edge of device clock and be sampled on rise edge with same order in the following SYSREF period.

    Regards

    Zhipeng
  • 0 in reply to Zhipeng lv
    TI__Guru* 91947 points
    Zhipeng,

    Yes, it can sampled on the second or third edge. Just make sure you turn off SYSREF after a few pulses.

    Regards,

    Jim
  • 0 in reply to jim s
    Intellectual 465 points
    Jim

    Thank you for your reply. I also have another question about the PAP. If the PAP is enabled. Does PAP monitor the input signal power all the time? If I set a low threshold value and the input signal ' ample is higher than it.Does the PAP alarm mid-level the output?

    Today I set a low threshold value, when I change the input signal ' ample, sometimes the config108 replied PAP alarm but sometimes doesn't.
    Is it mean that the user data has go through the fifo?

    Zhipeng.