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DAC38RF82EVM: On-Chip PLL Clock Mode (Connected to TSW14J56)

Part Number: DAC38RF82EVM

Hello,

I tried numerous of times to configure the DAC38RF82EVM with the GUI (CMODE3). I use the manual ('SLAU671A' section 2.1.4 DAC38RF8xEVM Configuration With On-Chip PLL(CMODE3)), but unfortunately there is no RF output signal on the spectrum analyzer visible. The boards are all connected onto a 5V power supply and USB (as described in the User's Guide).

Both boards are recognized by the GUI (green light is on), but when I try to send the described (384M data rate, 100k) single tone sequence of the TSW14J56 board (HSDC GUI) the following window appears:

Additionaly on the TSW14J56 Board the LED D8 (Mem Fail~) is lighted as well as LED D2 (Tx CLK).

TSW14J56 (HSDC GUI):

used firmware: DAC38RF8x_LMF_841

DAC38RF82EVM (Hardware configuration):

- JP2   (Shunt pin 1-2: Enable DAC output)

- JP10 (Shunt pin open: Enable on-chip PLL clock mode)

- SMA J4 (Ref Freq. 384M, 6dBm)

Since I use User's Guide configuration, what can be the source of the setup problem? Moreover, is it possible to get any additional information/documentation regarding the DAC38RF8x EVM GUI since there are a lot configuration options?

Kind Regards,

Ivan

  • Ivan,

    Make sure the TSW14J56EVM 5V supply can source at least 3 Amps.

    Regards,

    Jim 

  • Dear Jim,

    the hardware is connected in the same way as described in the User's Guide. The TSW14J56 is connected to a 5V/3A power supply. I used the J4 (LMK CLKin) input at DAC with 384 MHz/6dBm ref signal in order to set the sampling rate to 6144 MHz by using the On-Chip PLL option. After the configuration of the DAC I try to send a single tone pattern from the TSW14J56 GUI and I get:

    "Current lane rate is 3.84G. JESD reference clock from device EVM to TSW14J56revD needs to be set at 96M." (window text)

    I assume this is a notification and maybe it indicates that the TSW14J56 is missing a reference (at 96M) from the EVM. How can I proove this?

    Regards,

    Ivan

  • Ivan,

    After programming the DAC, did you run the PLL Auto tune then verify the PLL LF Voltage was set to either 3 or 4? If so, after this step, did you load the TSW14J56EVM with the DAC38RF8x_LMF_841 file? After the firmware is loaded and a test pattern sent, you will see the message you show above in your post. This means the LMK on the DAC EVM needs to provide a 96M clock to the TSW14J56EVM. It does not mean the clock is missing. After hitting send, you should see LED D2 (TX_CLK) blinking, and D3 and D8 illuminated on the TSW14J56EVM. Next click on the "Reset DAC JESD Core and SYSREF Trigger" button on the DAC GUI. You should now see a valid output from the DAC.

    Regards,

    Jim 

  • I have verified the PLL LF Voltage and at first it is set to 3 or 4, but after some time it goes back to 0. I loaded as well the DAC38RF8x_LMF_841 file to TSW14J56EVM. The LEDs are also illuminated as described.
    Now there is also some output at the DAC. The signal analyzer displays CW signals which can only be enabled/disabled by the Mixer at Digital(DAC A) tab. Signal analyzer output are CW signal (peaks) at multiple of about 400MHz. When I enable the NCO the signal disappears. So I am not able to set some NCO frequency.
  • Hi Ivan,

    You can verify the DAC is programmed correctly by using the constant data feature to output a tone. See attached screenshot for directions on how to output 1 GHz tone from DAC with the constant data and NCOs. If this works, try to increase current limit of bench supply to TSW14J56 EVM to 4A. But if you still have issues, send me your email and I will work with you to resolve this offline.

    Thanks,

    Eben.

  • This issue was resolved by changing the regional settings of the PC to English (United States)