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ADC12D1800: ADC12D1800 I road work abnormally

Part Number: ADC12D1800

In my project with an ADC - adc12d1800, Two channel sampling, Q road is normal, I road is abnormal.

Abnormal phenomena of the specific as follows: the noise test, observation from the XILINX-ISE-chipscope, DI and DID not overlap. Reset for many times, both the location of the instability.

This phenomenon appeared in the work after period of time.

Figure 1 is the normal phenomenon

Figure 2 and 3 is the abnormal phenomenon(blue-DI; green-DID; red-DQ and DQD)

What causes this phenomenon? Thanks for your help!

  • Hi

    The ADC12D1800 ADC uses an interleaved calibrated architecture. The I converter channel is made up of two interleaved ADCs, and the Q converter channel is made up of two interleaved ADCs. There are a total of 4 ADC cores on the device.

    When run under the proper conditions the built-in self-calibration process will optimize the linearity of the 4 ADC cores, and also match their full scale range and offsets. It may be that the calibration is being run before the ADC clocking and power have fully stabilized.

    Once the ADC is powered on, with stable clocking, re-run the self-calibration process. (see datasheet section 5.3.3).

    If this doesn't improve the offset matching between the DI and DId data, then the issue may be due to a stuck bit in the data interface between the ADC and FPGA data capture device. You can validate the interface by enabling the Test Pattern Mode and comparing the received data to that shown in Table 5-2 or 5-3.

    Best regards,

    Jim B

  • In reply to Jim Brinkhurst84999:

    Dear Jim B

    Thanks for your help! I'm very sorry, We still didn't solve the problem.

    First,the Test Pattern Mode I used in the past, there is no problem.

    Second,the On-Command Calibration is being run after the ADC clocking and power have fully stabilized.According to the datasheet recommends,after the PLL clock for ADC locked,I add almost 20s delay before  the calibration and do nothing during this time,the problem remains.In addition,I could catch the signal"CalRun"from low to high.

    The FPGA program in another same ADC board,didn't appear this problem.

    Do you have any Suggestions?Thanks!

  • In reply to user4076667:


    The behavior you are seeing with the I-channel data is unexpected. Have you observed this same behavior on just a single ADC device, or does this happen on multiple instances of your design?

    Can you provide the schematic showing all ADC connections including clock source, power, etc?

    Have you confirmed the ADC power supply voltages are within specification?

    Can you wait until the part goes into the abnormal mode and then enable test pattern mode to confirm the issue is definitely not in the data path?

    Can you provide the raw data in hex or decimal format on each output port of the ADC in the test pattern mode, normal data mode and abnormal data mode?

    Are you writing to any of the device configuration registers? If so can you provide the details of what is being written?

    Best regards,

    Jim B

  • In reply to Jim Brinkhurst84999:


    We have six boards with the same design,using the same program.The first time,all of them are normal.After about a month,there is only one abnormal.

    1.I can confirm all the power supply voltages for ADC is right.I compared it with a well board.

    2.As you suggest,I modified the program.After PLL clock locked,ADC goes into the  abnormal mode,then about 20s,enable test pattern mode. The phenomenon is the test pattern mode is right.

    3.Picture 1 is the abnormal board's raw data in hex on each output port of the ADC in the test pattern mode.

    Picture 2 is the abnormal board's raw data of noise in hex on each output port of the ADC in the standard mode.

    Picture 3 is the well board's raw data of noise  in hex on each output port of the ADC in the standard mode.

    4.Picture 4 is the register list.

    Thanks for your help!

    Ce Liang

  • In reply to user4076667:


    I will review the additional information. Are you able to provide schematics? If not can you confirm whether you are using AC-coupled or DC-coupled analog inputs?

    Is there any possibility that the analog input of the affected channel is getting some DC level applied?

    It may be that the single ADC exhibiting the problem has been damaged in some way. In that case you can submit it for quality evaluation by following the steps listed here:


    Best regards,

    Jim B

  • In reply to Jim Brinkhurst84999:


    I used AC-coupled analog inputs.Here is  a simplified schematic diagram.Please ignore "adc10d1500"in the schematic,I share packaging for this series.

    adc12d1800 board-simplified.pdf


    Ce Liang

  • In reply to user4076667:

    Hi Ce

    I have one more suggestion to try.

    I see that your connection from Vcmo to GND is 1k ohms. Can you change this to 0 ohms on the board with the issue, and let me know if anything improves? 1k ohms may be not quite low enough to reliably hold the Vcmo pin below the detection threshold to enable AC-coupled mode.

    If this doesn't help then I think you should submit that part for quality evaluation as mentioned earlier.

    Best regards,

    Jim B

  • In reply to Jim Brinkhurst84999:

    Hi Jim

    I have done as you suggested,but in vain.I'll change a new chip,and tell you the status in a few days.


    Ce Liang