Part Number: ADS54J66
I'm trying to calculate total latency of the ADC datapath with the JESD204B link operating in subclass 1 mode as shown in: e2e.ti.com/.../jesd204b-how-to-calculate-your-deterministic-latencyThe datasheet only shows an overall ADC sample to digital output data latency. The devices in the blog example instead show t_LAT-ADC (ADC sample to LMFC) and t_D-DATA (LMFC to digital output data) which allows the link latency to be calculated with the Rx delay parameters. Can you please provide the breakdown of the ADC latency with respect to LMFC?
After checking with the design team, I was informed we do not have latency info from ADC core alone. What the data sheet shows is total latency, including the Tx serializer. What is not shown in the datasheet is the latency of additional digital blocks such as gain or DDC filtering. Since the device uses FIR linear phase structures for DDC filters, the number of taps (or order) indirectly provide the delay information about DDC filter.
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