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ADC32RF45: SPI Question related to SDO?

Dan Van Winkle
Intellectual 320 points
Part Number: ADC32RF45

Hi,

I've got a design with two ADC32RF45's on it.  In the design I ran common clk, SDI, SDO wires to both chips.  That is, the clk lines are hooked together to one pin on the FPGA driving it, the SDI pins are tied together and so are the SDO pins.  The chip select pins are obviously not hooked together.

My problem appears to be that the SDO output does not appear to be reaching full voltage.  Have a look at the photo.  The yellow, red and green lines are the CS, SDI and CLK respectively.  The blue is the SDO and appears to be reaching about half it's output.  My question is, is it OK to tie the SDO's together, or will one of the SDO's pull the other low?  There is very little information on this actual interface in the datasheet, so it's hard to determine what's going on.  It's also quite possible that my FPGA guy has screwed up his pin assignments.  He told me just yesterday that he had SDI and SDO swapped, so who knows what else he's done wrong.  But as usual, firmware must be troubleshot with a scope :).

We can always run the chip in 3 wire mode if we need to, but I'd like to understand this problem.  If I did screw up by hooking the SDOs together, I want to fess up!

Thanks in advance!

.  

  • 0
    Intellectual 320 points
    It turns out when I un-hook one of the SDOUT pins, the logic rises to the proper output? So, it appears that despite the chip select, the non-accessed SDOOUT pulls down the output of the used SDOUT? Shouldn't the chip select put the non-accessed SDOUT in tri-state to allow multiple of these devices to share the same 4 wire bus? I think we will be able to run in 3 wire mode, but if I am correct in this assumption, then this chip is flawed in my opinion.
  • 0 in reply to Dan Van Winkle
    TI__Mastermind 29220 points

    Hi,

    Thank you for the follow-up findings.  I will take this to the design team for comment.  On our EVM we just have the one device, so the SDO pin is not being shared with other ADCs.  I scanned the datasheet and I do not see any statement that the SDO pin is high impedance when not outputting the read back data.   But I do see in the diagrams for the SDO format (figures 118 and 121, depending on revision of the datasheet) that the SDO is drawn as 'low' in the time leading up to the output of data, rather than what I sometimes have seen in other datasheets as drawn as mid-scale to indicate high impedance until the device is driving the readback data.  So it seems that the SDO pin is not high impedance when not in use.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Intellectual 320 points

    I'm pretty disappointed in TI for letting this part out with this flaw.  Luckily I only have 2 devices on board and was able to put an OR gate on the SDOUT pins.  In addition, my firmware guy was able to put it in 3 wire mode which seems to work fine.  You should add some information to the datasheet ASAP so that others don' screw up their designs using this VERY expensive part.

  • 0 in reply to Dan Van Winkle
    TI__Intellectual 2740 points

    Hello Dan,

    My name is Amanda Ross and I'm the local FAE contact supporting you and your team.

    Although our forums are the best way to get in contact with the specialists, I also wanted to provide my contact information so you have me as an additional resource for any future TI-related questions. Feel free to shoot me a message anytime.

    Best Regards,

    -Amanda Ross

    (a-ross@ti.com)

  • 0 in reply to Dan Van Winkle
    Prodigy 40 points
    Did you find any better way to work around this? It appears that if you put the device in 3-wire mode that it _still_ drives SDO, so while it "works" it means that it disrupts all other devices on the SPI bus unless you pull the connection to SDO.
  • 0 in reply to Erich Hoover
    Intellectual 320 points
    We ended up going back to 4 wire SPI and running the SDO to an OR gate. In the final design we ended up just running the SDO to a separate pin on our FPGA. Bothersome but workable.
  • 0 in reply to Dan Van Winkle
    Prodigy 40 points

    Thanks.  I guess it's time to cut some traces then :/

  • 0 in reply to Erich Hoover
    Intellectual 320 points
    Ya...my kludge wasn't pretty, but did work. The ADCs are working pretty well now. But..in case you didn't know...look at page 117. They have a very clever spur canceling circuit (offset correction), but it also cancels any signals you might have at those frequencies. The spurs are quite high (-50 dBc I've seen) . So, if you have signals around those frequencies be careful. I guess I should have read every page in the data sheet...
  • 0 in reply to Dan Van Winkle
    Prodigy 40 points
    Good to know, thank you. We're primarily interested in a signal at f_s/5, f_s/10, and f_s/15 - so hopefully we're good. If not then we'll have to get to know its nice little calibration feature ;)
  • 0 in reply to Erich Hoover
    TI__Mastermind 29220 points

    Hi,

    Yes, the SDO pin does not tri-state when the SPI is not enabled so the SDO cannot be bussed amongst a number of devices.   On our EVM we have three devices with SPI ports, (ADC and two clocking devices) and the clock and SDIO signals are bussed, but the enables get their own signal each and the readback gets their own signals each.   The USB device has 8 GPIO pins so that worked out - three SPI enables, three readback pins, a common clock and a common SDIO - for a total of 8.   I agree it would have been more flexible if the designers had thought to turn off the SDO driver when the device SPI was not enabled.

    Regarding the interleaving spurs, this is a function of the architecture of the ADC front end.   To get the 3Gsps sample rate in this process the front end is 4-way interleaved with four sub-ADCs sampling at up to 750Msps each.   And then there is digital logic to subtract out the DC offset of each sub-ADC.   But consider what happens when the input signal is right at 750MHz - it aliases back on top of DC for each sub-ADC.   And at this point there is the choice of subtracting out the DC offset and knocking out any frequency content at Fs/4 along with it, or allowing the frequency content at Fs/4 to remain but now the DC offset of each sub-ADC comes along for the ride.   They can't be separated out from each other after the ADC front end.   So integer multiples of Fs/4 will be subtracted out, and for that matter also integer multiples of Fs/8 but I haven't seen a similar line of reasoning for why Fs/8 gets the same treatment.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 40 points

    Thanks Richard, this is all great information.  I'm just really glad that it wasn't too hard to cut the SDO for our design, the next rev of our board will definitely have those split out separately.  With respect to the spur, that makes a lot of sense - I'll just have to see how much it impacts us when we get to that point.  However, it looks like our design team spec'd it out such that it won't be an issue for our application ;)