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ADS42LB69: ADS42LB69 clock out missing

Expert 1730 points
Part Number: ADS42LB69

Hello,

     In our design the data clock out is connected to an FPGA. Inside the FPGA (Kintex-7) the clock is first connected a IBUFDS and then a BUFG before being connected to the IDDRs (for the data bits) and some other circuits. 

The clock coming out of the BUFG is called adc_clk_bufds_bufg. This clock is connected to a PLL which has both locked and clock input stopped outputs. 

We suspect that there is no clock coming out on the data clock. Is there any register that has to be enabled to make this happen? Upon powering up, we only do a hardware reset. 

By default the device operates in DDR LVDS mode and so the data clock out should be the same as the sampling clock of the ADC which is 200MHz in our case. 

Thank you for your help,

Regards,

SM

  • SM,

    After a hard reset, you must write a 0x1 to address 0x15 to get the output clock running.

    Regards,

    Jim

  • Hello Jim,
    Thank you for the answer.
    We started testing the ADC output to FPGA Interface and observed the following:
    1) The ADC was configured to send out all 1s and 0s and the FPGA read them correctly.
    2) Then we tried the alternating pattern (register value 0x33) but we get alternate 0xFFFF and 0x0000 (some realignment of data is occurring)
    3) We tried the deskew pattern (0xAAAA), instead 0x5555 is being received
    4) 8-point sine wave: periodic values with period 8 are being received but all are incorrect.
    The problem is that we are not getting the correct data, so there is some data alignment issue.

    There is no problem of noise/timing in our opinion because the numbers do not change with time (we acquire data in snapshots of 1024 words at a time) and have done many runs

    We are interfacing this to a Xilinx 7 FPGA and the signal flow inside the FPGA is as follows:
    1) data goes to IBUFDS and then IDDR (we tried different configurations for the IDDR (opposite_edge, same_edge and same_edge_pipelined), the results are similar (all of them give incorrect values)
    2) clock goes to IBUFDS and then IBUFG (the adc_bit_clk_bufds_bufg is used as the clock source for the IDDR)
    The data bit clock has been put under timing constraints.

    Thanks again for your help,
    SM.
  • SM,

    Can you send us the complete register configurations you are using? Do you still this issue when running at a much slower sample rate?

    Regards,

    Jim

  • Hello Jim,

              Actually we are doing very little in terms of register settings:

    Hard reset the IC and then,

    1) Writing 0x01 to 0x15 (enabling DDR mode) 

    2) 0x03 to 0x0F (setting the ADC to send test pattern data)

    We haven't tried running the ADC at a lower sample rate because we didn't see any time varying change in the received data. 

    Regards,

    SM

  • Hello Jim,

              May I ask if we are missing anything in the register configurations? 

    Looking forward to your inputs,

    Regards,

    SM