Hello,
In our design the data clock out is connected to an FPGA. Inside the FPGA (Kintex-7) the clock is first connected a IBUFDS and then a BUFG before being connected to the IDDRs (for the data bits) and some other circuits.
The clock coming out of the BUFG is called adc_clk_bufds_bufg. This clock is connected to a PLL which has both locked and clock input stopped outputs.
We suspect that there is no clock coming out on the data clock. Is there any register that has to be enabled to make this happen? Upon powering up, we only do a hardware reset.
By default the device operates in DDR LVDS mode and so the data clock out should be the same as the sampling clock of the ADC which is 200MHz in our case.
Thank you for your help,
Regards,
SM