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TSW14J10EVM: Incompatibility between KC705, TSW14J10EVM, and ADC32RF45EVM

Robert Banks
Intellectual 330 points

Part Number: TSW14J10EVM

Hello,

I am working with a system that utilizes the KC705, TSW14J10EVM, and ADC32RF45EVM to process an analog system with custom FPGA firmware. I have found that many of the JESD lanes do not actually connect to the FPGA instead they end at the FMC connector on the KC705 board.

I bought this board because it stated compatibility with the KC705 board but it looks like this is not the case. To make sure that I wasn't crazy I looked up the schematic for the VC707 board and sure enough, all the lanes are connected.

If this is truly incompatible, I recommend removing the KC705 board from the list of compatible boards.

Thanks,

Robbie

  • 0
    TI__Genius 12965 points
    Hi Robbie,

    You are correct that the KC706 does not route all 8 lanes of the JESD204B interface, only 4 of the lower lanes. This means that the KC705 can only work with devices with JESD204B modes utilizing the lower 4 lanes.

    Can you be specific about which document indicates the ADC32RF45EVM will work properly with the TSW14J10+KC705? The TSW14J10 can be used with KC705, VC707, ZC706 and KCU105 directly using our HSDC Pro software. Checking the INI files for eack of the platforms, it only shows ADC32RF45 INIs for the VC707, ZC706, and KCU105. These are the official Xilinx platforms that have been tested to work with the ADC32RF45/80 (these INIs are from that validation).

    Please let us know where the error is so that we can make the corrections.

    In some cases it is possible to only interface to a part of the JESD204B lanes. For example of there are 2 channels in a device and the lower 4 lanes are used for channel 1 and upper 4 lanes are used to channel 2 samples, it is possible to only interface to the lower 4 lanes OR the upper 4 lanes and ignore the other lanes. You could then only extract the samples associated with those lanes.

    Ken
  • 0 in reply to Ken C
    Intellectual 330 points
    Hi Ken,
    Here is the link to the web page which makes it seem as though this adapter board will work:
    www.ti.com/.../tsw14j10evm

    This is the wording:
    Provides the interface between High Speed Data Converter EVM’s and FPGA Development board through two FMC connectors.
    Xilinx KC705, ZC706 and VC707 platforms.

    Unfortunately, when the lanes get routed out from the ADC32RF45, the lower lanes from the ADC are connected to where the upper lanes would be for FPGA with the exception of 1 lane.

    Thanks,
    Robbie
  • 0 in reply to Robert Banks
    TI__Genius 12965 points
    Robbie,

    Thanks - we will look into making this more clear.

    Ken.