ADS5484: ADS5484

Hi,

The minimum and maximum sample rate for the ADS5484 is listed in the datasheet as from 10Msps to 170Msps.  So the sample clock can be from 10MHz to 170MHz.  The data clock output named DRY will be exactly the same frequency as the sample clock.  The 16 bit sample data is output on 8 LVDS pairs in DDR (Dual Data Rate) fashion as in figure 1 of the datasheet.   The rising edge of the output clock will be used to register the even numbered bits of the sample and the falling edge of the output clock will be used to register the odd numbered bits of the sample.   So if the sample rate were 170MHz, then the output clock would also be 170MHz but the data rate of the LVDS signals carrying the data would be twice that at 340 Mbps due to the DDR nature of the sample bus.    (Note please that the output clock DRY is source synchronous with the data transitions.  This means that the FPGA receiving the digital bus must perform a 90 degree delay of the DRY signal before it can be used to latch the data bits with the rising and falling edges.)

The datasheet lists the minimum and maximum voltage swing for the LVDS outputs, and minimum requirements for inputs.  How long an LVDS trace could be will depend on the loss characteristics and quality of the routing of the material, and the minimum requirements of the device that will be receiving the signals.  What that maximum length would be cannot be determined in advance just by the specifications of the ADC.  It would need to include the specs of the other devices and the geometry and material for the signals in between.    And also data rate - the slower you choose to run the clock rate the longer the traces could likely be.  It is common to see the

Regards,

Richard P.