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ADS54J69: JESD204B interface

Part Number: ADS54J69
Other Parts Discussed in Thread: ADS54J60

I am designing in an ADS54J69 ADC into a custo0m circuit board and the JESD204B interface on this chip is somewhat confusing.

The datasheet for the ADS54J59 chip shows 4 high speed transmit lanes for each of the two on board  ADC channel - these being DA0, DA1, DA2 & DA3 for channel A etc.

However, the datasheet also clearly states that only 1 lane at 10 Gbps (or 2 at 5.0 Gbps) are needed. So basically what are the remaining two lanes for? Why have they been included in the chip package  if they are never  used? At 500 MSPS, the maximum data rate will be 8 Gbps - so clearly we do not need 4 JESD lanes.

Second issue, if only 2 lanes are actually needed at 500 MSPS, I am assuming that we need to connect  only the DA0 and DA1 for channel A  (DB0 and DB1 for channel B) to the FPGA and can leave the DA2 and DA3 (DB2 and DB3) lanes unconnected? Is there any subtle reason why I should connect all 4 lanes to the FPGA?

Lastly, are there any reference IP designs for integrating the ADS54J69 into a Xilinx FPGA flow? The TI eval board uses Altera FPGA which is not helpful.

Thanks

  • Raoul,

    Per the Feb 2016 data sheet revision, you can only use either 4 lane mode or 2 lane mode. At the max sample rate of 500Msps, 4 lane mode will run at 5Gsps and 2 lane mode will run at 10Gbps. Not sure where you got your numbers from. 

    If you need a slower serdes rate with respect to your ADC sample rate, you would normally use more JESD lanes. This part gives you the option to do this. If for a particular sample rate, you only need two lanes, the device allows this as well. The number of lanes you use is up to the user as long as the serdes rate is within spec of the device.

    For example firmware code, go the TSW14J10EVM product folder on the TI website. You can download the code from here. There is also example code on the Xilinx website. Both locations have examples for the KC705, VC707, and ZC706.

    For Ultrascale firmware, here is a link to 1.3 of the UltraScale Hardware Demo on the Xilinx JESD lounge.

     

    http://www.xilinx.com/member/jesd204_eval/JESD204B_UltraScale_Hardware_Demo_2016_1_v1.3.zip

     

    Regards,

     

    Jim

  • Jim

    Not sure if we are seeing the same thing. I am looking at page 1 of the 2016 ADS54J69 datasheet and under the "Features" heading it says very clearly the following, and I copy:

    Also on page 32, it clearly says the same and I copy:

    Hence my question and confusion. Keen to get your feedback on this. If I am reading this datasheet correctly,  do not think you can operate this ADC with four lanes as you  have indicated above.

    Thanks

    raoul

  • I copied and pasted sections from the datasheet to my previous reply, but they do not seem to have been included when I posted the message.

    So in words:

    From page 1, I quote:

    JESD204B Interface with Subclass 1 Support:
    – 1 Lane per ADC at 10.0 Gbps
    – 2 Lanes per ADC at 5.0 Gbps
    – Support for Multi-Chip Synchronization

    From page 32, I quote:

    Depending on the ADC output data rate, the JESD204B output interface can be operated with either two or four
    active lanes (out of total 8 lanes), as shown in Figure 71. The JESD204B setup and configuration of the frame
    assembly parameters is controlled via the SPI interface.

  • Raoul,
    Page 1 is a typo. This will be corrected with the next revision of the data sheet.
    Regards,
    Jim
  • Typos on datasheets leave me extremely uncomfortable as they are the foundation on which decisions are made and custom hardware is built. So to repeat, you are saying that both pages 1 and 32 are incorrect? When can I expect a corrected datasheet?
    As a sanity check, can you please confirm with your colleagues that the datasheet is incorrect? I would really appreciate that.
  • Raoul,

    I was wrong with my last email. This part will only support 1 or 2 lanes per ADC. Lanes DA2,DA3, DB2, and DB3 are not used. The data sheet is correct as is. The wording may be a little confusing though.

    Regards,

    Jim 

  • Jim
    So that comes back to my original question. Why did TI engineers decide to pin out all four lanes per ADC, if only 2 lanes max can ever be used? This issue bugs me.
  • Raoul,

    The ADS54J69 is the same part as the ADS54J60 but modified to remove the bypass option. Bypass required all 8 lanes. This is why the other lanes are not used. 

    Regards,

    Jim

  • Jim
    Following up on our conversation, I have some further questions,
    I am looking at TI's SLAU711 user guide, which discusses using HSDC Pro with Xilinx KCU105 boards

    The Xilinx firmware referenced on page 3 of the user guide is generic firmware that internally loopbacks all eight JESD204B data lanes within the FPGA - so you cannot hook it up to any EVM modules. It is just meant to evaluate the Xilinx JESD204B IP cores in a loopback configuration. - unless significant modifications are made to customize it.

    On page 7 of the user guide, a reference is made to the Xilinx IP core that actually interfaces to any of TI's JESD204B boards is made. However it seems to be available only as a bit file - i.e. see the reference to "KCU105_TI_DHCP.bit" under the heading "Programming the FPGA". I would like to get access to the Xilinx Vivado project that generated this bit file. The reason is that I need to port this fully functioning design to a custom Xilinx board. Any help?
    Thanks
    Raoul
  • Raoul,

    This firmware is located on the Xilinx website (see section 2 from User's Guide shown below). There is a parameter that allows the firmware to either target loopback mode, TI EVM's or ADI EVM's. See note below.

    Regards,

    Jim

    2 Functionality

    The KCU105 has a standard FMC connector that proves an interface between FMC-based development

    boards and all TI JESD204B ADC and DAC EVMs. For communicating, the KCU105 uses Ethernet to

    acquire and receive data, and do register read and writes using a host PC across a Serial Peripheral

    Interface (SPI). The KCU105 has a dual USB-to-UART bridge interface for system control as well as

    reading necessary information such as the board IP address. The KCU105 also has an industry-standard

    JTAG connection for configuring the FPGA using the Vivado® Design Suite, a design tool by Xilinx.

    The firmware designed for this integration is used to support HSDC Pro, communication through SPI, and

    any TI FMC-based JESD204B EVM at any line rate. This user's guide is a starting point, but the firmware

    is over complicated for designing a regular system. The firmware is located at the following Xilinx web site:

    www.xilinx.com/.../uhwd_2016_3_v1_0.zip. The zip file includes documentation

    of an example design that can be generated in Vivado 2016.3. In the Vivado project, the firmware can be

    stripped down and designed for a more practical system.

    NOTE: Run the command set TARGET "TI" before creating the project to generate TI bitstreams.

     

     

  • Raoul,

    The version of source code used by the TI EVM's with the KCU105 can be downloaded from the link below.

    Regards,

    Jim

    txn.box.com/.../bjozlhvj3lbtx15r15wiec6pm864vtie

  • Jim

    I downloaded Xilinx reference JESD204 IP design, ran the  "build_it.tcl" tcl file located in the scripts folder using the Vivado tools and successfully generated the output bit file. So there were no issues there - i.e. pretty straight forward. The tools build the loopback test by default.

    I could not find any reference in the documentation for  that special parameter you mentioned above  that allows you to target different vendor boards - i.e. any of  TI's FMC development boards. What is that parameter and how is it set? Can you point it out to me?

    Thanks

    raoul