Other Parts Discussed in Thread: ADS54J60
I am designing in an ADS54J69 ADC into a custo0m circuit board and the JESD204B interface on this chip is somewhat confusing.
The datasheet for the ADS54J59 chip shows 4 high speed transmit lanes for each of the two on board ADC channel - these being DA0, DA1, DA2 & DA3 for channel A etc.
However, the datasheet also clearly states that only 1 lane at 10 Gbps (or 2 at 5.0 Gbps) are needed. So basically what are the remaining two lanes for? Why have they been included in the chip package if they are never used? At 500 MSPS, the maximum data rate will be 8 Gbps - so clearly we do not need 4 JESD lanes.
Second issue, if only 2 lanes are actually needed at 500 MSPS, I am assuming that we need to connect only the DA0 and DA1 for channel A (DB0 and DB1 for channel B) to the FPGA and can leave the DA2 and DA3 (DB2 and DB3) lanes unconnected? Is there any subtle reason why I should connect all 4 lanes to the FPGA?
Lastly, are there any reference IP designs for integrating the ADS54J69 into a Xilinx FPGA flow? The TI eval board uses Altera FPGA which is not helpful.
Thanks