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ADS52J90: Relation between SYSREF and LMFC

masahiko shimizu
Guru 11235 points
Part Number: ADS52J90

Hi,

My customer is using ADS52J90.

My customer thinks a frequency of SYSREF clock must be a multiple frequency of LMFC clock.
If a frequency of SYSREF clock is not a multiple frequency of LMFC clock, What is happen?

Best regards,
Shimiuz

  • 0
    TI__Expert 4145 points

    Hi Shimizu-san,

    We have received you inquiry and will get back to you at the end of the week.

    Sincerely,

    Olu

  • 0 in reply to Olu Sodipe
    TI__Expert 4145 points
    Hi Shimizu-san,

    What customer is this for and what is their application?

    Sincerely,
    Olu
  • 0 in reply to Olu Sodipe
    Guru 11235 points
    Hi Olu-san,

    Thank you for your support.
    I send E-mail about this.

    Best regards,
    Shimizu
  • 0 in reply to masahiko shimizu
    TI__Expert 4145 points

    Hi Shimizu-san,

    Thanks for the email. If SYSREF frequency is not a multiple of LMFC frequency, then SYSREF can be asserted in the middle of a multiframe which can lead to JESD devices resetting and the link not coming up. 

    Sincerely,

    Olu

  • 0 in reply to Olu Sodipe
    Guru 11235 points
    Hi Olu-san,

    I add questions about this.

    Cold you please let me know why JESD devices is reset at SYSREF frequency which is not a multiple of LMFC frequency?
    I think that this causes by setting of JESD_RESET register. Is this correct?

    And

    Could you let me know the mean of "JESD BLOCK" at Table 27 and Table 28 in datasheet, please?
    Does "JESD BLOCK" mean only clock timing? or include the something of register setting?

    Best regards,
    Shimizu
  • 0 in reply to masahiko shimizu
    TI__Expert 4145 points

    Hi Shimizu-san,

    JESD block refers to the JESD TX block as per Figure 72 on Page 49.
    Having a continuous SYSREF signal that is not a multiple of the LMFC frequency means that the JESD link will continually have to reset the phase of the LMFC every time the SYSREF is sampled at the rising edge of the device clock .i.e. continuously restarting a multiframe in the middle of another multiframe.

    The JESD204B standard goes into more information about SYSREF, LMFC and multiframe alignment.

    Sincerely,
    Olu

  • 0 in reply to Olu Sodipe
    Guru 11235 points

    Hi Olu-san,

    Thank you for your reply.
    I ask other questions for understanding your answer.

    Q1: If having a continuous SYSREF signal that is a multiple of the LMFC frequency, Is JESD Block reset?
    Q2: If the reset occur at having a continuous SYSREF signal that is a multiple of the LMFC frequency, Do ADS52J90 and FPGA re-negotiation for link?

    Best regards,
    Shimizu

  • 0 in reply to masahiko shimizu
    TI__Expert 4145 points

    Hi Shimizu-san,

    If you want to gain a deeper understanding of how SYSREF works within JESD204B, I recommend going over this material.

    In addition, most FPGA vendors (Altera, Xilinx) have their own proprietary IP that determines FPGA, JESD TX interaction. 

    Sincerely,

    Olu