TSW14J56EVM: Migration to an independent FPGA (ALTERA) design

Shai,

We are looking into this.

Regards,

Jim

Shai,

This is from our software design team:

Every time Capture button is pressed in HSDC Pro, JESD Base IP "Jesd204b_mc_rx", Native PHY IP "xcvr_native_rx" and PLL "jesd_avgz_rx_pll" in the firmware gets reconfigured. In this process the IPs are put in reset and after reconfiguration they are brought out of reset.

JESD link is re-initialized in every capture and this was done so that the firmware can support dynamically different lane rates and different JESD Link configuration (different LMF values). As the IPs are coming out of reset in every capture, SYSREF is required for each capture

Description of JESD Base IP, Native PHY IP and resets required are mentioned in the Altera reference documents.

https://www.altera.com/en_US/pdfs/literature/ug/ug_jesd204b.pdf

https://www.altera.com/en_US/pdfs/literature/ug/xcvr_user_guide.pdf

The above reconfig process on capture button press can be skipped if the lane rate and JESD LMF values don't change from the previous capture

Please follow the steps mentioned below to skip reconfig process after first capture

• ·         Make a copy of the ini file specific for the particular ADC mode

This file will be available in HSDC Pro installation directory "\High Speed Data Converter Pro\14J56revD Details\ADC files" folder

Default location is "C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J56revD Details\ADC files"

• ·         Add the ini parameter "skip reconfig=1" below the place where JESD IP Core parameters are listed in the ini file
• ·         Restart HSDC Pro, Select the original ini file in the ADC ini files drop down, input the ADC sampling rate and do a capture
• ·         This will configure the JESD BaseIP, PHY IP and PLL for the particular ADC reference clock and the particular JESD Link configuration
• ·         Now select the new ini from the ini drop down and click capture, this will not reconfigure the IPs and the JESD link will not be re-initialized.

This new ini can be used for all the subsequent captures

Regards,

Jim

Hello Jim,

Thank for this reply.
This description provides us good insight to the sequence of operations performed during Capture event.
However, I would like to emphasize that our intention is to be totally independent of the HSDC Software, since that the target FPGA / ADC board is not going to support any USB connection.
In this target board, the only relevant mode of ADC operation is the BYPASS mode.
We tried to associate the given configuration file (ADC12J4000_BYPASS.ini) with all necessary modifications of parameters values in the mentioned ALTERA IPs.
Although some IP parameters seem to be straightforward (e,g, JESD IP Core_CS=0, ESD IP Core_F=8, ...), other at not (e.g. JESD IP Core_Tailbits=4?, JESD IP Core_LaneSync=1?, JESD IP Core_Lane_Enable=255?).
The preferred implementation, from our point-of-view, will be to synthesize the ALTERA FPGA design with new set of static parameters, which exactly fits the requirements this ADC12J4000 BYPASS mode.
Using this approach, we expect that the only extra operation needed will a generation of a SYSREF signal.
So the question is, how can we obtain the precise set of IP parameters modifications with respect to the existing reference FPGA design?

Regards,

Shai

Shai,

For this, I would suggest using the TSW14J56EVM to display the JESD204B parameters used by the IP. I have attached an example with the ADC12J400 in bypass mode sampling at 4G. The parameters used by the IP are shown in the second slide.

Regards,

Jim

Display JESD Parameters.pptx

Hello Jim,

Now the JESD204B ALTERA IP is pre-configured with the exact set of parameters, as displayed by the HSDC Window - "Board Dynamic Configuration Parameters" as you suggested.
Moreover, we commented out most of the lines in the relevant file: ADC12J4000_BYPASS_SERDES.ini, and are able to successfully capture the ADC Ramp Test Pattern.
There is an issue of "Bit Packing Channel Pattern" configuration, which we need to understand, but it could be skipped at the moment.
The HSDC SW "Capture" is still required, so the issue is unresolved yet.
It might be related to a required Reset cycling of the ALTERA IPs?
In that case, what is the correct reset sequencing required?

Regards,