ADS54J69: JESD204B Lane Usage When 2x Decimation Is Not Used

Richard Elmquist

Part Number: ADS54J69
Other Parts Discussed in Thread: ADS54J60

The data sheet shows the lane usage and bit assignments when using JESD204B (Figure 74) but this is only shown if 2x decimation is used. Do we have a diagram that shows the lane assignments etc. if 2x decimation is not used?

Thanks for your help with this!

Richard Elmquist

over 6 years ago

0 Jim Brinkhurst1 over 6 years ago

TI__Mastermind 43860 points

Hi Richard
I'm looking into the question.
I should have a response by sometime tomorrow.
Regards,
Jim B

0 Jim Brinkhurst1 over 6 years ago in reply to Jim Brinkhurst1

TI__Mastermind 43860 points

Hi Richard
It turns out the datasheet for the ADS54J69 is somewhat confusing regarding the decimation feature, but this device always operates in Decimate-by-2 mode. With the maximum rated 1 GHz input clock, the effective output sample rate is 500 MSPS.
The ADS54J60 is a similar device which supports the Decimate-by-2 mode, but also includes undecimated and
Decimate-by-4 modes of operation. Raw ADC sampling rates of 250 to 1000 MSPS are supported with this device.
Best regards,
Jim B

0 Richard Elmquist over 6 years ago in reply to Jim Brinkhurst1

TI__Mastermind 45250 points

Jim,

Thanks so much for your help!

I will let you know if the customer has any further questions.

Have a great weekend.

Richard Elmquist

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ADS54J69: JESD204B Lane Usage When 2x Decimation Is Not Used