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TSW14J10EVM: Matched Length

ikon
Genius 5355 points

Part Number: TSW14J10EVM

Hi Support,

With reference to TSW14J10 schematic Page 4 attached... 

Does SYSREF has to be length-matched with GTX_CLKP/M or CLK_LA0_0P?
Note that on the FPGA, GTX_CLKP/M goes to the GTH high-speed transceivers to which the high-speed serial lanes are also connected.
CLK_LA0_0P/M are connected to a normal MRCC bank on the FPGA.

Thanks.

Adaptor card schematic.pdf

  • 0
    TI__Mastermind 43930 points
    Hi ikon
    The SYSREF and CLK_LA0_0 signals should be length matched. These are for the JESD204B SYSREF and DEVCLK, which should have a defined timing relationship. the GTX_CLK signal is used for the transceiver PLL reference clock so any skew between that signal and the SYSREF or DEVCLK is not critical.
    Best regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    Genius 5355 points

    Hi Jim,

    Thanks for the info.

     

    With reference  to TI  DAC 38J84 schematic, ( see attachment ) length match is require for the GTX_CLK and SYSREF . The is no length match requirement for CLK_LA0. This is different from the interposer spec.

     

    Need your advise which length match spec is correct.  

     

    Thanks.


  • 0 in reply to ikon
    TI__Guru* 91947 points

    Ikon,

    An early version of firmware was created by Xilinx which required both a core clock and reference clock. In most cases, this second clock (core clock, CLK_LA0 ) is not needed. When it was used, it was not required to have the same trace length as SYSREF. CLK_LA0 is not used with the Altera IP.

    Regards,

    Jim  

  • 0 in reply to jim s
    Genius 5355 points

    Hi Jim,

    It was mentioned previously that CLK_LA0 and SYSREF need to be length-matched. But now, its mentioned that the CLK_LA0 is not required at all and that even if it were required, it doesn’t have to be matched with SYSREF.

    Please address this contradiction. So, GTXCLK need not be matched with SYSREF at all?

    Thanks.

  • 0 in reply to ikon
    TI__Mastermind 43930 points

    Hi ikon

    I think some of the apparent contradiction is happening because of the different FPGA usages of the CLK signals.

    In general, if the respective clock signal is used for Core Clock or Core Clock and transceiver Reference Clock, then it should be length matched to the SYSREF path.

    If the clock signal is only used for the transceiver reference clock then it does not need to be matched as the exact phase of the reference clock is not critical, only the frequency.

    I hope this is helpful.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    TI__Guru* 91947 points

    Ikon,

    When using the firmware provided by Xilinx with HSDC Pro and either the VC707, KC705 or ZC706, SYSREF is captured with core_clk. So if you are using a separate core_clk, which this firmware does, then this is the clock that is critical to capturing SYSREF and should have the same length as SYSREF. The other clock (refclk) does not matter because it is only the reference for the PLL.

    If using refclk as core_clk (which can sometimes be the case) then refclk to SYSREF is critical and has to be matched length.

     

    Regards,

     

    Jim