Thanks Jim,

But I can understand reason of 3rd register and also How do you assign Even and Odd data to forth register with ADC OUTCLK?

could you explain more about this schematic?

Regards,

Amir

Hi Jim,

When I see the output of ADS 5463EVM, there is some discontinuously waveform in output. Actually I used differential to single end buffer inside the Zynq chip and converted all output and DRY to single end then I connected these signal directly to output pins of Zynq SOC, so I have captured the output with digital logic analyzer, It shows there is some discontinuously when there is no input. below picture showes the outputs without input for ADC (J11 on EVM board is open)

and the below picture is zoomed one of these discontinuous.

as you see there is a same change for all bits at the same time for one clock period, the lower signal is the DRY signal. I don't know what is the reason. what do you think?

Amir,

What sample rate is the clock at? Do you see this problem if you use a slower clock speed?

Regards,

Jim

for this experimental, clock rate is 220MHz, and there is same problem in both lower and higher than this clock speed, of course for higher frequency density of these discontinuity is increasing.

Jim, did you receive my message?

Amir,

Yes and we are looking into this. What is the IF input frequency and amplitude? Are you using filters on both the clock and IF inputs?

Regards,

Jim

Amir,

How long are your data traces? Are they matched length both the P/N and pair to pair? Have you tried capturing the data using a clock that is twice the rate of DRY? In this case you could use the falling edge only of this faster clock (if this meets setup and hold time inside the FPGA). Also see page 36 of the data sheet for more information about the output timing.   

Regards,

Jim  

Hi Jim,

I know you have verilog or VHDL code for TSW1200, could you send this code for me? maybe it can solve more problems for me as an example.

Regards,

Amir

Jim,

Based on below link, TI was using Xilinx fpga on TSW1200 Capture Card and your college  Richard P have sent this code for your customer.

e2e.ti.com/.../1198754

please check this page.

Thank you,

Amir,

The TSW1200 is longer supported. Are you asking for the firmware used by this board? If so, I can try to locate it.

Regards,

Jim

Not firmware, I need just verilog or vhdl code for TSW1200 Capture Card.

TSW1200 Source Serial v1p5.zipTSW1200 Source Parallel DDR ver1p6.zipAmir,

Firmware is usually associated with Verilog or VHDL source code. I have attached what I could find. Hope this helps.

Regards,

Jim

Hi Jim,

So appreciate for your attachment, I am using IDDR same your firmware but after IDDR I am trying to assign pso and neg edge data to one register but  I couldn't secede do you have any solution?

Best Regards,

Amir

Amir,

All of our firmware developers are tied up with other customer issues and development work for new products. I will submit a request for them to look at this but would suggest you contact your local Xilinx FAE in the mean time to see if they can offer any assistance.

Regards,

Jim

Hi Jim,

I could capture ADC output for 400Mhz with static timing solution. now I am going to capture with 500Mhz But for 500Mhz static timing dose not work and I have to use dynamic calibration to capture the proper data, I don't have any idea about dynamic calibration do you have any source about this topic? or could you explain for me briefly about dynamic calibration?

Thank you so much,

Amir