Other Parts Discussed in Thread: DAC5687, DAC5688
Dear to anyone who can help me out
I'm struggling with DAC3482 on my custom board for days, but all the trials have been found to be unsuccessful. The test conditions and the observed results are as follows.
1. Test conditions
1) Operational parameters
- Data clock : 100MHz
- DAC clock : 100MHz (External, no interpolation(1x) and NCO disabled)
- FIFO synchronization : Single sync source mode, all synchronous with non-periodic FRAME (dual mode also tested, but the result was the same)
- Data format : Word-wide
- Test input : Sine wave at the freq. of 100000000/1024Hz(=97.66kHz)
2) Register settings & configuration sequence
REG Value
0 0x009C
1 0x000E
2 0xF082
3 0xA000
7 0xD8FF
12 0x0400
13 0x0400
20 0x0000
21 0x5000
24 0x2808
26 0x0020
27 0x0800
9 FIFO offset (properly chosen which doesn't issue the FIFO collision alarm)
31 0x1110
32 0x2201 (and TXENABLE goes HIGH)
5 0x0000 (Loop the last 4 lines until any FIFO collision no longer occurs)
2. The results
1) Alarm FIFO 1 or 2 Away always occurring
2) The output waveform badly distorted (
3) Sawtooth shape periodic of 16 data clock cycles in the output observed
4) Pictures captured (Please look at the envelope but never mind the glitches since I think I can take care of them by adjusting clock phases later)
Thank you for your concerns!
best regards,
Shim