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DAC38RF82: Unable to generate signal from DAC: single tone only.

Part Number: DAC38RF82

I’m trying to get correct transmission from a custom board with a DAC38RF82 on-board.  However with a DAC clock of 9000MHz, the only thing I can get the DAC to do is either a constant frequency of 2250MHz or (with different settings) a constant frequency of 562.5MHz.  I think I’m missing something on the setup of the chip or setup of the JESD communication, but the DEC indicates everything is working correctly – I just can’t get the start of a signal related to the JESD communication out of the device as a starting point to work from.  Any help would be appreciated.

The setup is as follows:

The chip is connected to a Xilinx Kintex-7 FPGA, which generates the JESD204 signal with a rate of 7.5Gbps on 8 lines to the DAC chip.  I’ve tested the JESD204 signal using a spectrum analyser and it appears to be trying to send a signal.  The input clock to the DAC chip is 375MHz to both the DACCLK pins and to the SYSREF pins.  I’m using the onboard PLL to generate the 9000MHz reference DAC frequency (M=6, N=1).  The DAC mode is Single (DAC A), 1 IQ Pair with 6x interpolation.  

I've attached a file which has the screen shots from the evaluation board equivalent settings.  The actual messages I send are as follows (Hex,  ADDRESS (2 characters), DATA (4 characters))

                          x"090000",   

                           x"007860",

                           x"011880",

                           x"0200FF",

                           x"0300FF",

                           x"090004",

                           x"0B0000",

                           x"1B0100",

                           x"0CA002",

                           x"241001",   

                           x"310400",

                           x"320508",

                           x"33C318",

                           x"3BA802",

                           x"3C8229",

                           x"3E0109",  

                           x"090001",

                           x"0A0310",

                           x"0C2600",

                           x"0D0301",

                           x"0F1F83",

                           x"190001",

                           x"1E1111",

                           x"1F1111",

                           x"201111",

                           x"256300",

                           x"2D1FFF",

                           x"2E1FFF",

                           x"320800",

                           x"330800",

                           x"4AFF03",

                           x"4C1307",

                           x"4D0101",

                           x"4F1CE0",

                           x"51001F",

                           x"090002",

                           x"0A03B0",

                           x"0C2402",

                           x"256300",

                           x"4C1307",

                           x"4D0101",

                           x"090000"

 

Testing is as follows:

Power rails have been tested and are working.   I can output the downsampled by 80 PLL output clock, and the frequency looks good.  The alarms indicate that the main DAC PLL is locked and the SERDES PLL is locked.  All the alarms for the JESD look good (no lane or fifo errors), also with a detection of signal on all lanes.  However the only way I get the DAC is to output anything is to enable the mixer on the AB path.  When this is done, I get a continuous tone of 562.5MHz (along with harmonics).  Also if I untenable the QRCLOCK_DACA_ENA setting, it will produce a 2250MHz signal.  Nothing seems to be using the signal output from the JESD.  I just can’t see what’s going wrong and have run out of options to test.  Any help would be appreciated.  DAC38RF82_Test_Settings.docx

  • Bryan,

    Using Chipscope,can you verify all 8 lanes of the FPGA are passing CGS and ILAS and sending valid data? Is the SYNC from the DAC going high and staying high after this sequence? Is TXENABLE high?

    Regards,

    Jim  

  • I've tested the 8 lanes from the FPGA and it has moved past the CGS and ILAS and is sending valid data.  The SYNC from the DAC is high, and TXENABLE is high.  Testing the lane conditions it indicates it's all ok.  

    One question I have is for clock configuration register 0x0A, should the QRCLOCK_DACA_ENA be high or low?  For the messages sent from your evaluation board it is high, however to me it should be low.  However I can't get anything to work properly under the low condition. 

    Also I've started testing setting the input to be "constant input" just for testing.  When I do that I can enable the NCO and get things to work a bit more (can create a line spectrum around 600MHz, with 37.5 MHz spacing, however it still isn't making much sense.  

  • Also one extra little thing is that for the NCO, it appears that the sin and cos lookup table is designed for 2's compement only. It seams to produce a bunch of harmonics if you assume offset binary.
  • Probing the errors more, it appears that I have the error states "EQUNDER" and "EQOVER" at the same time. May need to reset these and read in more detail that section of the data sheet.
  • Bryan,

    I got our setup running with your settings. It required an external 375MHz reference clock to the LMK. For register 0x0A, the value used was 0x7C03. All of the register settings can be found in the attached file. See if this helps you.

    Regards,

    Jim

    Fs_9000_821_PLL_REF_375MHz.cfg

  • Hi Jim,

    Thanks for the configuration file, it should help a lot.  To further help, could you indicate the sequence of buttons you would press to get the chip working?  Would you just press load configuration file on the application, or would you also press some extra buttons e.g. "Configure DAC" etc to get it to work.  Just working out all the resets and other settings that need to be defined.

    Thanks,

    Bryan 

  • Hi Jim,

    Still unable to progress on this chip at all... really feel like I'm banging my head against a brick wall.  All alarms seam good, and I've added your setup the same as your configuration file.  However, with the same result - nothing coming from the transmitter.  I've monitored the JESD204 signal, and it changes when I change the transmission signal.  However no change in the DAC output, when the JESD204 signal changes.  I can get a oscillation from the DAC by enabling the mixer, but that's it.  I've also tried testing the JESD204 signal using the TESTPATT with a 0/1 pattern and then using DTEST to output the result, however I can't get any success, and it's not giving me any information to tell me what I'm doing wrong.  For test this I input a "01010101" pattern into all the i/q values for the 82121 frame.... but I'm not sure if this is the right way to do this.  

    I'm think I have an issue with the JESD204.  I'm using the standard Xilinx IP core, but there is very little to adjust within the core, so I can't see what's wrong.  Would you have any example code under vivado that would help?  I've been trying to get this chip working for over 5 weeks now, and I'm starting to think it's impossible.

    Regards,

    Bryan   

  • Also if I send a signal such as all "0"s on the JESD204 signal for the I and Q, it produces a very liney spectrum with 37.5MHz between the lines.... This doesn't make sense. Also a different code (e.g. "000111111000") will produce a 375MHz line spectrum. It's all rather weird to me... the coding really doesn't make sense as it doesn't look like 8B/10B.
  • Now I think about it, it may be to do with the multi-frame settings of 20.
  • Bryan,

    Make sure the value of K is the same on both ends and that the following is true per the JESD204B standard:

    17 < F*K < 1023

    Regards,

    Jim 

  • Bryan,

    Which Xilinx FPGA are you targeting? We have examples of Xilinx source code using the KC705, VC707, and ZC706 under the TSW14J10EVM product folder on the TI website. There is also some examples using the KCU105 on the Xilinx website. See the attached document for more info regarding interfacing our ADC's and DAC's with the Ultra-scale parts.

    Regards,

    Jim

    1588.KCU105 HSDC Pro User's Guide.pdf

  • Thanks for the example code.... helps a bit, but much more complicated, so trying to break it down.

    Looking at my code, I'm thinking it could be the AXI4-lite interface.  I had assumed that this was redundant and the core wizard would set things up correctly in the first place, so I had left the interface unconnected (gnd etc), apart from the clock the reset lines.  It seams like the core wizard does set up the number of lanes, but I'm not sure if it changes the default K of 16 to 20 and the octets (F) from 2 to 1.  Working on this now.

    Would you know if in your example code this had to be done?

  • Bryan,

    This is what I got from my Xilinx contact regarding your questions:

    "If the customer sets the correct values for F and K in the IP GUI, then these will be used as the default value for cores registers.

    This means the customer should not need to program these registers.

     

    Do they know if the core is actually transmitting data..?

    (probing a serdes line with a spectrum analyser will not tell them this ;-)

    A really good clue is…

    Is there dataflow into the core on (tx_tready high and tx_tdata changing)

    If not then….

    Have the JESD204 core and JESD204_PHY come out of reset?? (Read the reset register via the JESD204 core AXI lite interface)

    Have the JESD204 PHY, pll’s locked?? (This info is available via the PHY AXI lite interface)

     

    The TX core is quite simple. It only needs to come out of reset and achive sync. Then it will start to transmit."

    Can you send me your entire DAC configuration file and I will try it on our setup? Are you following everything in the start-up sequence section 9.1.1?

    Regards,

    Jim

  • I’ve added an interface to the AXI and have probed its status.  It all looks good.

     

    AXI interface results:

    Register                               x004 – reset done

                                                    X008 – ILA support enabled.

                                                    X00C – no scrambling

                                                    X010 – all ‘0’s

                                                    X014 – 3

                                                    X018 – all ‘0’s

                                                    X020 – 0

                                                    X024 – “10011” (19)

                                                    X02C – subclass 1

                                                    X038 – “00000000000000010000000000000001”

     

    However for X80C to X81C, all I am getting is all ‘0’s.  Not sure why?

    Going through the entire sequence of 9.1.1, and it all looks good.  LFVOLT = 4.  I end up with the same VCO tune value as you got (C5).  Everything response as expected. 

    The SPI command I am sending are as follows, which is the same as what you sent. (Address followed by Data “AAAADDDDDDDD”)

                               x"090000",

                               x"005860",  --x"007860",     -- enable output of alarm

                               x"013080",  --x"011880",

                               x"FF0000",   -- it holds in this state until the system is working.

                               x"02FFFF",

                               x"03FFFF",

                               x"0400FE",

                               x"050003",

                               x"060002",

                               x"780000",

                               x"790000",

                               x"7A0000",

                               x"7F0008",

                               x"FF0000",                             

                               x"090004",

                               x"0A7C03",

                               x"0B0002",

                               x"0CA002",

                               x"0DF000",

                               x"1B0000",  -- x"1B0100",

                               x"23FFFF",

                               x"241001",   

                               x"310400",

                               x"320508",

                               x"33C53C",

                               x"340000",

                               x"350018",

                               x"3BA802",

                               x"3C8229",

                               x"3D0088",

                               x"3E0909",

                               x"3F0052",   -- needed to invert some lines.

                               x"090001",

                               x"0A0310",

                               x"0C2402",

                               x"0D0000", --x"0D0301",

                               x"0E00FF", -- x"0EFFFF",

                               x"0FFFFF",

                               x"10FFFF",

                               x"11FFFF",

                               x"120000",

                               x"170000",

                               x"190001",

                               x"1C0000",

                               x"1D0000",

                               x"1E0000",

                               x"1F0000",

                               x"200000",

                               x"210000",

                               x"220000",

                               x"230000",

                               x"240030",

                               x"256300",

                               x"278888",  -- x"272222",

                               x"280330",  -- x"280220",

                               x"290000",

                               x"2A0000",

                               x"2B0000",

                               x"2C0000",

                               x"2D1FFF",

                               x"2E1FFF",

                               x"2F0000",

                               x"300000",

                               x"320400",

                               x"330400",

                               x"340000",

                               x"350000",

                               x"360000",

                               x"370000",

                               x"380000",

                               x"390000",

                               x"3A0000",

                               x"3B0000",

                               x"3C0000",

                               x"410000",

                               x"460044",

                               x"47190A",

                               x"4831C3",

                               x"4AFF03",

                               x"4B1300",

                               x"4C1307",

                               x"4D0101",

                               x"4E0F4F",

                               x"4F1C60", --x"4F1C41",

                               x"500000",

                               x"51001F", --x"5100FF",

                               x"5200FF",

                               x"530100",

                               x"548E60",

                               x"5C0002",

                               x"5E0000",

                               x"5F0123",

                               x"604567",

                               x"640000",

                               x"650000",

                               x"660000",

                               x"670000",

                               x"680000",

                               x"690000",

                               x"6A0000",

                               x"6B0000",

                               x"6C0000",

                               x"6D0000",

                               x"6E0000",

                               x"090002",

                               x"0A0310",

                               x"0C2402",

                               x"0D0000",

                               x"0E00FF",

                               x"0FFFFF",

                               x"10FFFF",

                               x"11FFFF",

                               x"120000",

                               x"170000",

                               x"190001",

                               x"1C0000",

                               x"1D0000",

                               x"1E0000",

                               x"1F0000",

                               x"200000",

                               x"210000",

                               x"220000",

                               x"230000",

                               x"240020",

                               x"256300",

                               x"278888",

                               x"280330",

                               x"290000",

                               x"2A0000",

                               x"2B0000",

                               x"2C0000",

                               x"2D1FFF",

                               x"2E1FFF",

                               x"2F0000",

                               x"300000",

                               x"320400",

                               x"330400",

                               x"340000",

                               x"350000",

                               x"360000",

                               x"370000",

                               x"380000",

                               x"390000",

                               x"3A0000",

                               x"3B0000",

                               x"3C0000",

                               x"410000",

                               x"460044",

                               x"47190A",

                               x"4831C3",

                               x"4A0003",

                               x"4B1300",

                               x"4C1307",

                               x"4D0101",

                               x"4E0F4F",

                               x"4F1C60",

                               x"500000",

                               x"51001F",

                               x"5200FF",

                               x"530100",

                               x"548E60",

                               x"5C0003",

                               x"5E0000",

                               x"5F0123",

                               x"604567",

                               x"640000",

                               x"650000",

                               x"660000",

                               x"670000",

                               x"680000",

                               x"690000",

                               x"6A0000",

                               x"6B0000",

                               x"6C0000",

                               x"6D0000",

                               x"6E0000",                         

                               x"090001",

                               x"240000",

                               x"5C0000",

                               x"090004",

                               x"0AFC03",

                               x"0A7C03",

                               x"090000",

                               x"005863",

                               x"090001",

                               x"240020",

                               x"5C0003",

                               x"090000",

                               x"005860",

                               x"040000",

                               x"050000",

                               x"090003",

                               x"640000",    -- clear

                               x"650000",

                               x"660000",

                               x"670000",

                               x"680000",

                               x"690000",

                               x"6A0000",

                               x"6B0000",

                               x"6C0000",

                               x"6D0000"                                                                                                                                                                                

     

    The JESD204 core is out of reset and the PLL locked output is going high as expected.

    All the alarms are indicating that the chip is working. 

                    Page 0, 0x4 = all ‘0’s

                    Page 0, 0x5 = all ‘0’s

                    Page 1, 0x64 to 0x6D = all ‘0’s

                    Page 2, 0x64 to 0x6D = all ‘0’s  (not that this is important)

                    Page 4, 0x76 = all ‘0’s.

    Also I can see the TData changing.  On top of this if I probe the JESD204 lines with a spectrum analyser when operating, I can see a change in the spectrum changing when I change what I am sending on the data lines.

    The sysref to the dac is a 375MHz signal.  The sysref to the FPGA is a 23.44MHz signal.  Not sure about these?

    In general, I’m trying to get anything out of the DAC, at this point I really don’t care what it is…. Just as long as it is something related to what I am sending via the JESD204b interface.

    All the voltages to the chip are correct.

    I’ve tested another board, with the same results – not a soldering issue.

    Not sure what else to do?  

  • Hi Jim,

    I've spent the day trying to get the 8-bit mode working, with an input frequency of 1500MHz directly to the DAC (no pll), but equally having the same problem.... can't get a output signal directly unless I enable the mixer, and then only a single frequency (93.75MHz).  

    I'm using a custom board, not the development board, so I am unable to send you the configuration file directly.  I'm following the startup sequence, apart from the following points:

    1) The power rails start up before TXENABLE is pulled low.

    2) TRSTB pin is tied to ground so I can't control it.

    All the rest I'm doing as per 9.1.1 (I think).

    Any help would be appreciated.

    Regards, Bryan

  • Bryan,

    Restb needs to be toggled after power up and the DAC CLK is applied. Keeping TRSTB low is fine. I ran your setup with a value of 20 for both K and RBD. Please try this with your setup. With this value of 20 for K, the max rate for SYSREF is 75MHz. I used a value of 3.125MHz for this. I would try the lower rate to keep your setup as close as possible to mine. If you had K = 20, using SYSREF at 375MHz may have been your problem. Can you send a copy of your schematic? Are your Serdes lanes routed the same as the EVM?

    Regards,

    Jim  

  • Hi Jim,

    Thank you for your help, yes it was the SYSREF signal being too high (375MHz).  I change the settings so that the SYSREF was less I initially tried 3.125MHZ, but it was a bit too slow for the clock gen chip for some reason, so I ended up going to 11.71875 MHz - 3000MHz / 256, which now works well every time.

    I really appreciate your support and thank you for detecting the issue.... these chips are quite complicated and it's difficult getting through all the elements of the data sheets.  I owe you a beer next time I'm in the states ... or the next time you're in Australia (brisbane).

    Regards,

    Bryan