Hello,
I am having issues getting the lanes working with this device.
I am using the mode LMFSHD = 4,4,2,1,0 with k(frames per multiframe) = 10 and an input clock of 100MHz with no interpolation and DAC PLL in bypass. My SYSREF is 2.5MHz. TRSTB is held low and TXENABLE is held high.
Through a test mode I have verified that the FPGA is sending k28.5 characters at a bit rate of 2gbps. During normal operation I can see that the SYNC is being lost and resync is being attempted.
When I read the alarms I get the DACPLL out of lock, Serdes PLL 1 out of lock and Lane errors of 0x0F03 for all 4 lanes. When I initialize the demo board I get the same PLL lock errors and so I'm assuming that is fine since I am bypassing the DACPLL and not using Serdes PLL 1. I will also note that I am able to get the demo board working with very similar settings. The main difference being the different frequency and lane swapping.
Here is my initialization sequence:
// Disarm CLK divider and JESD links
0x02, 0x2002
0x24, 0x0000
0x5C, 0x0000
// DAC PLL Setup (Disabled)
0x1A, 0x0020
0x31, 0x1000
0x32, 0x0000
0x33, 0x0000
// SerDes Setup
0x3B, 0x0000
0x3C, 0x0228
0x3D, 0x0088
0x3E, 0x0108
0x3F, 0x0000
// JESD Setup
0x46, 0x0044
0x47, 0x190A
0x48, 0x31C3
0x49, 0x0000
0x4A, 0x0F1E
0x5F, 0x0123
0x60, 0x4567
// JESD Setup
0x03, 0xA300
0x25, 0x0000
0x4A, 0x0F1E
0x4B, 0x0901
0x4C, 0x0903
0x4D, 0x0300
0x4E, 0x0F0F
0x4F, 0xBCC1
0x50, 0x0000
0x51, 0x00FF
0x52, 0x00FF
0x53, 0x0000
0x54, 0x00FF
0x55, 0x00FF
0x5C, 0x1103
0x5F, 0x0123
0x60, 0x4567
0x61, 0x0111
//DSP Setup
0x00, 0x0018
0x01, 0x0003
0x02, 0x2002
0x03, 0xA300
0x04, 0xF0F0
0x1E, 0x9999
0x1F, 0x9980
0x20, 0x0000
// Arm CLK divider
0x24, 0x0030
// Arm JESD Link0
0x5C, 0x1103
// Pull JESD out of reset
0x4A, 0x0F1F
// Pull JESD out of initialization state
0x4A, 0x0F01
Any help would be appreciated.
Thanks,
Robbie