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DAC39J84: JESD Lane Errors

Part Number: DAC39J84

Hello,

I am having issues getting the lanes working with this device.

I am using the mode LMFSHD = 4,4,2,1,0 with k(frames per multiframe) = 10 and an input clock of 100MHz with no interpolation and DAC PLL in bypass. My SYSREF is 2.5MHz. TRSTB is held low and TXENABLE is held high.

Through a test mode I have verified that the FPGA is sending k28.5 characters at a bit rate of 2gbps. During normal operation I can see that the SYNC is being lost and resync is being attempted.

When I read the alarms I get the DACPLL out of lock, Serdes PLL 1 out of lock and Lane errors of 0x0F03 for all 4 lanes. When I initialize the demo board I get the same PLL lock errors and so I'm assuming that is fine since I am bypassing the DACPLL and not using Serdes PLL 1. I will also note that I am able to get the demo board working with very similar settings. The main difference being the different frequency and lane swapping.

Here is my initialization sequence:

// Disarm CLK divider and JESD links
0x02, 0x2002
0x24, 0x0000
0x5C, 0x0000

// DAC PLL Setup (Disabled)
0x1A, 0x0020
0x31, 0x1000
0x32, 0x0000
0x33, 0x0000

// SerDes Setup
0x3B, 0x0000
0x3C, 0x0228
0x3D, 0x0088
0x3E, 0x0108
0x3F, 0x0000

// JESD Setup
0x46, 0x0044
0x47, 0x190A
0x48, 0x31C3
0x49, 0x0000
0x4A, 0x0F1E
0x5F, 0x0123
0x60, 0x4567

// JESD Setup
0x03, 0xA300
0x25, 0x0000
0x4A, 0x0F1E
0x4B, 0x0901
0x4C, 0x0903
0x4D, 0x0300
0x4E, 0x0F0F
0x4F, 0xBCC1
0x50, 0x0000
0x51, 0x00FF
0x52, 0x00FF
0x53, 0x0000
0x54, 0x00FF
0x55, 0x00FF
0x5C, 0x1103
0x5F, 0x0123
0x60, 0x4567
0x61, 0x0111

//DSP Setup
0x00, 0x0018
0x01, 0x0003
0x02, 0x2002
0x03, 0xA300
0x04, 0xF0F0
0x1E, 0x9999
0x1F, 0x9980
0x20, 0x0000

// Arm CLK divider
0x24, 0x0030
// Arm JESD Link0
0x5C, 0x1103
// Pull JESD out of reset
0x4A, 0x0F1F
// Pull JESD out of initialization state
0x4A, 0x0F01

Any help would be appreciated.

Thanks,

Robbie

  • Robert,

    We are looking into this. What FPGA are you using?

    Regards,

    Jim

  • Hi Jim,

    I'm using a Kintex-7.

    Thanks,

    Robbie

  • Robert,

    I got our EVM running with your settings. I have attached the LMK and DAC register settings. This has the DAC sampling at 100MHz, no interpolation, 4 lanes, SYSREF = 2.5MHz, K = 10 and scrambler disabled. I am using DAC inputs  RX0-RX3 but in reverse order as that is how they are routed on our EVM. The registers that contain lane ID information may not match up with your system but all the other settings should. See how these register settings compare to what you are using. If needed, we have example Xilinx source code that we used to test our DAC EVM with a KC705 development board.

    Regards,

    Jim

    Fs_100M_LMF_4421.cfg 

  • Hi Jim,

    Thanks for looking into this for me. The example Xilinx code would help a lot. I'm thinking that we either have a solder problem, a schematic problem, or VHDL problem and this code could eliminate another unknown.

    Thanks,

    Robbie

  • Robert,

    You can find the example code under the TSW14J10EVM product folder on the TI website. There also is example code on the Xilinx website.

    Regards,

    Jim

  • Great, thank you.
  • Hi Jim,

    We were able to resolve the lane errors. As it turns out, our JESD core within the FPGA was not being clocked from the same source as the JESD in the DAC. This caused the lane errors since the two clocks weren't phase locked.

    Now there are no errors but the DAC isn't outputting anything expected. The output sits at about 1V with a 50ohm load. I have tried setting the DAC to output a constant value but the output does not change. Can you think of a reason that this might happen? I am currently investigating the hardware again for schematic issues but maybe I missed something in the register settings. To output a constant value I do the following:

    1. Initialize the clocks
    2. Initialize the DAC with the normal settings
    3. Write register 0x2F to 0x0005
    4. Write register 0x02 to 0x2000
    5. Write register 0x30 to any number

    Thanks,
    Robbie

  • Robert,

    A better test is to use the NCO as an output tone generator. To use the NCO as an output, you need to write the following:

    add 0x02     0x2050

    add 0x2F     0x01

    add 0x14, add 0x15, add 0x16  (this is the DAC clock frequency and NCO frequency)

    add 0x17  0x1140

    add 0x17 0x1142

    add 0x17 0x1140   (This sequence is to synchronize the NCO) 

    If you can get an NCO output, this verifies the DAC is receiving power, clock and SYSREF properly and the SPI is working. How is TXENABLE configured? This must be high for the DAC to provide a valid output. 

    Regards,

    Jim

  • Hi Jim,

    I tried using the NCO to generate a tone and still nothing. TXENABLE is pulled high and sif_txenable is also set. To verify that SYSREF is working, I disabled it from the clock chip and verified that I get lane errors. Then I re-enabled it and the lane errors went away.

    Thanks for the tone test. I'll use it once I figure out what is going on. I suspect that it is hardware related. Maybe in the power supplies as you mentioned.

    Thanks,
    Robbie

  • We were finally able to get output. As it turns out, the Rbias resistor wasn't placed on the board even though it shows that it should be placed on the schematic.