ADC12DJ3200: Cannot lock for ADC12DJ3200

Mickey Zhang

Genius 12080 points

Part Number: ADC12DJ3200

Hi team,

The customer uses ADC12DJ3200. The power supply is fine. But when the input clock is 2.4GHZ,

the PLL_LOCKED bit of the JESD_STATUS register is 0. This mean PLL is not locked.

Would you explain this?

Best Wishes,
Mickey Zhang
Asia Customer Support Center
Texas Instruments

over 6 years ago

0 Brian2001 over 6 years ago

TI__Intellectual 2750 points

Hi Mickey,
I am sending this over to an engineer familiar with the device.
Regards,
Brian

0 Jim Brinkhurst1 over 6 years ago in reply to Brian2001

TI__Mastermind 43870 points

Hi MIckey
How is the customer configuring the EVM for the 2400 MHz case? The default GUI software doesn't support this specific frequency.
Are they using an external clock at 2400 MHz, or using a TI provided configuration file to operate the on-board clocking at 2400 MHz.
Can they provide screen shots showing the configuration steps they are following with the ADC12DJxx00EVM GUI?
Best regards,
Jim B

0 Mickey Zhang over 6 years ago in reply to Jim Brinkhurst1

TI__Genius 12080 points

Hi Jim,

The customer does not use our EVM, he uses his board. You mean ADC12DJ3200 cannot support 2.4GHZ input clock frequency?

0 Jim Brinkhurst1 over 6 years ago in reply to Mickey Zhang

TI__Mastermind 43870 points

Hi Mickey

The ADC will support any clock frequency from 800 MHz to 3200 MHz as long as the differential input clock is clean and stable, is AC-coupled and meets the amplitude requirements listed in the datasheet.

Please provide the register settings (values and order of loading) they are writing to the ADC.

Best regards,

Jim B

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ADC12DJ3200: Cannot lock for ADC12DJ3200