ADC12DJ3200EVM: KCU105 Reference Design Targeted for ZCU102 Byte Ordering

I modified the KCU105 reference design to conform to the ZCU102 dev kit.  I am able to see an aligned ramp pattern across all lanes but when I try to sample a terminated input the samples out of the TI transport code looks off (and out of the JESD core itself).  I have the following:

The Lane Data out of the core does match what come out of the transport layer.  I am suspicious there is a lane mismatch or something similar.  The out of sequence occurrence appears to be synchronous.  The image below shows that.

The reference design mapping is confusing so I may be interpreting something incorrectly but I have tried a few iterations.  Below is what I mapped for the reference design.  

I then mapped the ZCU102

I do not understand the KCU105 mapping as the DA/DB buses don't appear to align to the MGT Quad IOs.

Lastly the only way I was able to achieve ramp alignment and incrementing is to use 2 JESD cores in the FPGA, which then matched all JESD parameters, like L.  The outputs are concatenated and fed to the transport code for sample extraction. 

Any insights into what might be wrong is greatly appreciated.  

Thank you!