ADS54J42: DC bias differences between "taps" out of ADC

Hi Tony, I have sent this to an engineer with experience on the ADS54J42
Regards,
Brian

Tony,

Do you issue a hard reset after power up? This is required of the device. Each channel consists of 4 ADC's. Each ADC will have a slightly different offset. This is why you are seeing 4 different values for each of the four samples. How does your overall captured output look? Can you send your register settings?

Regards,

Jim  

Hi Jim,

Yes, we reset the ADC after power up. The overall captured output looks good. We have tested using sine, square, and triangle waves as inputs. Everything looks good. The only anomaly we see is the DC bias between taps. Below is the code that initializes the ADC registers. Thanks for the help.

WriteBuffer[0] = 0x40;
WriteBuffer[1] = 0x03;
WriteBuffer[2] = 0x00;
XSpi_Transfer(SpiInstancePtr, WriteBuffer, NULL, 3);

WriteBuffer[0] = 0x40;
WriteBuffer[1] = 0x04;
WriteBuffer[2] = 0x68;
XSpi_Transfer(SpiInstancePtr, WriteBuffer, NULL, 3);

// Make register setting take effect (and enable JESD analog section?)
WriteBuffer[0] = 0x60;
WriteBuffer[1] = 0x00;
WriteBuffer[2] = 0x01;
XSpi_Transfer(SpiInstancePtr, WriteBuffer, NULL, 3);

WriteBuffer[0] = 0x60;
WriteBuffer[1] = 0x00;
WriteBuffer[2] = 0x00;
XSpi_Transfer(SpiInstancePtr, WriteBuffer, NULL, 3);

WriteBuffer[0] = 0x40;
WriteBuffer[1] = 0x04;
WriteBuffer[2] = 0x69;
XSpi_Transfer(SpiInstancePtr, WriteBuffer, NULL, 3);

WriteBuffer[0] = 0x60;
WriteBuffer[1] = 0x00;
WriteBuffer[2] = 0x80;
XSpi_Transfer(SpiInstancePtr, WriteBuffer, NULL, 3);

WriteBuffer[0] = 0x60;
WriteBuffer[1] = 0x01;
WriteBuffer[2] = 0x02;
XSpi_Transfer(SpiInstancePtr, WriteBuffer, NULL, 3);

WriteBuffer[0] = 0x60;
WriteBuffer[1] = 0x06;
WriteBuffer[2] = 0x0F; //?
XSpi_Transfer(SpiInstancePtr, WriteBuffer, NULL, 3);

WriteBuffer[0] = 0x60;
WriteBuffer[1] = 0x07;
WriteBuffer[2] = 0x08;
XSpi_Transfer(SpiInstancePtr, WriteBuffer, NULL, 3);

WriteBuffer[0] = 0x40;
WriteBuffer[1] = 0x03;
WriteBuffer[2] = 0x00;
XSpi_Transfer(SpiInstancePtr, WriteBuffer, NULL, 3);

WriteBuffer[0] = 0x40;
WriteBuffer[1] = 0x04;
WriteBuffer[2] = 0x6A;
XSpi_Transfer(SpiInstancePtr, WriteBuffer, NULL, 3);

WriteBuffer[0] = 0x60;
WriteBuffer[1] = 0x16;
WriteBuffer[2] = 0x02;
XSpi_Transfer(SpiInstancePtr, WriteBuffer, NULL, 3);

WriteBuffer[0] = 0x60;
WriteBuffer[1] = 0x17;
WriteBuffer[2] = 0x40; // reset PLL
XSpi_Transfer(SpiInstancePtr, WriteBuffer, NULL, 3);

WriteBuffer[0] = 0x60;
WriteBuffer[1] = 0x17;
WriteBuffer[2] = 0x00; // reset PLL
XSpi_Transfer(SpiInstancePtr, WriteBuffer, NULL, 3);

Tony,

What do you mean by ‘tap’ exactly? Does tap essentially mean receiver’s connection to a ‘lane’? Are you analyzing DC value on different lanes of the receiver? Can you make a figure to explain this in more detail? If your output looks fine, why is this a concern?

 

Regards,

 

Jim

 

Hi Jim,

Sorry for the confusion. Let me try to explain a little better. A 'tap' is one ADC sample stream coming out of the JESD204 receiver. My JESD204 receiver outputs four samples at a time at 100 MHz, thus four 'taps'. The ADC sample rate is 400 MHz. Let's call the outputs from my JESD204 receiver A, B, C, and D. If my input is a slow sine wave, and I take all the samples that come out of A, I get a perfect looking sine wave (that was sampled at 100 MHz). If I look at B, I get the same thing but the samples of B were collected one 400 MHz clock later than A. Same for C and D. So, when I am done I have four separate streams of data that were collected at 100 MHz. Now, I need to combine them to produce my 400 MHz sample stream. I do this by taking A0, then B0, C0,D0, A1, B1, C1, D1, A2, etc. The problem is that the A stream has a different DC bias than the B stream. The B stream has a different DC bias than the C stream, etc. I need to remove these biases in order to get a 400 MHz sample stream that looks correct.

I don't believe that this DC bias has anything to do with 'lanes' or anything in the digital domain. I am assuming that the ADC and the JESD204 receiver are communicating properly. I'm just looking at the data coming out of the JESD204 receiver. In fact, I wouldn't even know how to look at data on the 'lanes' without a JESD204 protocol analyzer connected between the ADC and the JESD204 receiver.

I hope this has clarified things. If not, let me know. Any ideas on the DC bias source and how to fix it? Thanks for the help.

T

Hi Jim,

I went back and read the entire thread. Earlier you said "Each channel consists of 4 ADC's. Each ADC will have a slightly different offset. This is why you are seeing 4 different values for each of the four samples.". I think that's what we are talking about. I guess I was surprised to see that offset difference as large as 150 counts. Is there a worst case spec on this? I didn't see it in the datasheet. Thanks.

T

Tony,

This part has a DC offset correction engine that should take care of these offsets. There are certain registers that can freeze this function. Please send us the entire register configuration you are using so we can see if this is the case with your part.

Regards,

Jim

Hi Jim,
It will take me a little time to be able to read all the registers out of the device. The non-default register programming sequence was previously posted in this thread on Mar 27. Is this enough information for you? Can you give more detail on which registers can freeze the offset correction function? Thanks.