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ADC3444EVM: Phase Difference vs. Power

Part Number: ADC3444EVM
Other Parts Discussed in Thread: ADC3444, DAC3162EVM

I have a customer asking the following about the ADC3444EVM:

The ADC3444 is connected with a TSW1400 board to receive a pattern of sine wave (fixed frequency, fixed amplitude), as source onto the input of the ADC.  This input varies from 0.1 to 1 full-scale of the ADC.

The captured ADC data is then post-processed in Matlab to extract the phase information.  We expect a constant averaged phase value from each pattern and that does NOT seem to be the case we are experiencing here.

Note: p10 and FS are 0.1x FS and 1x FS, respectively.  X-axis power input vs. Y-axis measured phase value (independent of the input signal amplitude).

Please provide any insight into the issue we are experiencing and advise any possible experimental test method.

I have a report that the customer produced, but I cannot post it on the WEB. Please let me know where I can send it.

Thanks for your help with this!

Richard Elmquist.

  • Hello Richard, I have sent this over to an engineer that works with the ADC3444
    Regards,
    Brian
  • Brian,
    Have you heard anything from the other engineer on this?
    Thanks for your help with this!
    Richard Elmquist
  • Brian,
    Can you ask the engineer if he needs the report the customer produced pertaining to this issue in order to understand what is happening?
    Can you ask them if they can give me an idea of when they might be able to offer a response?
    Thanks for your help with this!
    Richard Elmquist
  • Brian,
    Have you heard anything from the engineer that is looking at this issue?
    Please let me know when he might be able to respond so that I can give the customer an idea of when to expect some information from us.
    Thanks for your help with this!
    Richard Elmquist
  • Richard,

    In the post, what does the customer mean by "Note: p10 and FS are 0.1x FS and 1x FS, respectively.  X-axis power input vs. Y-axis measured phase value (independent of the input signal amplitude).:?

    What value at the analog inputs is 1 x FS? Is this 1Vp-p or 2Vp-p? What frequency is this input? Is this phase value issue between channels or for a individual channel? Per the data sheet, the input swing should not exceed 2Vp-p with a max input of 450MHz and 1Vp-p with a max input of 600MHz. Does the part go into over range during this test at full scale input? There is a feature to monitor the LSB as an OVR indicator. Is the phase issue appear to be more towards the max input range of the analog input?

    Regards,

    Jim

     

  • Jim,
    Thanks for your response.
    I will get the answers from the customer and post them as soon as possible.
    Thanks for your help with this!
    Richard Elmquist
  • Jim,

    Here are the answers from the customer:

    I have attached a copy of his report:

    ADC3444EVM_Phase Difference vs. Power_DAC_ADC_AM_PM-1_5_11_18.pdf

    What does the customer mean by:

    Note: p10 and FS are 0.1x FS and 1x FS, respectively.  X-axis power input vs. Y-axis measured phase value (independent of the input signal amplitude)

    "p10" = 0.1 x 1.0Vpp = 0.1xFS = 90mV approx.

    X-axis covers a discrete range of input power from 10% to 100% of FS input signal level, at a step of 10% increase

    Y-axis is the measured output of the ADC

    What value at the analog inputs is 1 x FS? Is this 1Vp-p or 2Vp-p?

    1Vp-p

    What frequency is this input? Is this phase value issue between channels or for a individual channel?

    10MHz

    Individual channel

    Per the data sheet, the input swing should not exceed 2Vp-p with a max input of 450MHz and 1Vp-p with a max input of 600MHz.

    Within spec.  at 1Vp-p

    Does the part go into over range during this test at full scale input? There is a feature to monitor the LSB as an OVR indicator. Does the phase issue appear to be more towards the max input range of the analog input?

    A single 10MHz CW of sine wave used as an input; its amplitude varies at a discrete step as mentioned above.

    Please let me know if you have any further questions for the customer.

    Thanks for your help with this!

    Richard Elmquist

  • Richard

    I have sent this off to the design team. I have also ordered an EVM to try this test in the lab. Can you see if the customer's issue follows the source by swapping the two inputs from  the splitter? What do they mean by AM-PM effect? Can they send a graphical representation of the test pattern? I have no idea what they are talking about when they mention 0.6 and 1.2 degree phase value. Can they send the test pattern so we can duplicate their setup?

    Regards,

    Jim

  • Jim,
    Thanks for your response!
    I will get the information from the customer and send it to you as soon as I can.
    Thanks for your help with this!
    Richard Elmquist
  • Jim,

    Here is the information from the customer:

    ADC3444_Truong_Olympus_5_14_18.docx

    I have also attached an excel file of the test pattern:

    troung_excel_testpattern.csv

    Please let me know if you have any further questions for the customer.

    Thanks for your help with this!

    Richard Elmquist

  • Jim,
    Are there any updates on this issue?
    Can you give me a time frame as to when you might be able to respond?
    Thanks for your help with this!
    Richard Elmquist
  • Richard,

    I am still waiting to here back from the design team. I do not fully understand the customer's issue based on the info they sent. Can you find out, in simple terms, if this is what they are seeing: When sending a common input to two  channels of the ADC, they are noticing the outputs are shifting in phase when the amplitude of the signal changes.

    Regards,

    Jim

  • Jim,
    I will ask and respond back as soon as I hear from him.
    Thanks for your help with this!
    Richard Elmquist
  • Jim,

    Here is the customer's response:

    Yes.  They seem to be on the right track there. For our application, an unexpected (or random) phase shift is translated into an incorrect and inaccurate result, measured at the output of the ADC conversion as input amplitude changes.

    Does this help? Can the designer offer any help?

    Thanks for your help with this!

    Richard Elmquist

  • Jim,
    Are there any updates on this?
    Thanks for your help.
    Richard Elmquist
  • Richard,

    Here is the latest response from the design team regarding this:

    "From the description of problem, it seems that customer is generating two sinewaves with preprogrammed phase difference (say 0.6 rad, 1.2rad or so) from a DAC

    and feeding them to channel 1 and 4 of ADC.

    The phase difference at output of ADC seems to me different by a small amount (<1degree) and seems to change with input power.

     

    However, he says he tries to ascertain if the problem was DAC’s output itself. He gives a not-very-clear description about what he did

    Excerpt from his word document:

    In this experiment, did he remove the ADC and connected DAC output directly to where?

     

    Can he clarify?

     

    Can he switch off ADC dither and retry his experiment?

    Regards,

    Jim

  • Jim,
    Thanks for the response.
    I will have the customer repeat the tests with the changes recommended by the designer.
    I will respond back when I hear from the customer.
    Richard Elmquist
  • Jim,

    Here is the response from the customer:

    From the description of problem, it seems that customer is generating two sine waves with preprogrammed phase difference (say 0.6 rad, 1.2rad or so) from a DAC and feeding them to channel 1 and 4 of ADC.

    The phase difference at output of ADC seems to me different by a small amount (<1degree) and seems to change with input power.

    However, he says he tries to ascertain if the problem was DAC’s output itself. He gives a not-very-clear description about what he did. Can he go into more minute detail?

    To isolate the issue the ADC is removed.  The same data pattern used to drive the DAC is now fed directly into our Matlab analysis code for phase computation.  This data injection point in Matlab normally takes its input from the output of the ADC in .csv for post-processing when ADC is used, but it is now being bypassed.  It is reading the DAC pattern directly instead. Also this test is used as a sanity check to make sure this phase variation is not from the algorithm itself, with the ADC not in the loop.  
     
    In this experiment, did he remove the ADC and then connected the DAC output directly to where? Can he clarify? Can he switch off ADC dither and retry his experiment?

    I will try this one.

    Please let me know if you have any further questions from the customer.

    Thanks for your help with this!

    Richard Elmquist

  • Jim,

    I forgot to send the results of the tests:

    Please let me know if you have any further questions.

    Thanks for your help with this!

    Richard Elmquist

  • Richard,

    It seems customer is feeding Matlab code to DAC then to ADC.

    When he bypasses the DAC and ADC to check sanity, he directly feeds matlab code to his phase computation software.

     

    How is customer ensuring that DAC output itself is not having phase mismatch when its output power increases?

    Regards,

    Jim

  • Jim,
    Thanks for your response!
    I will reply back as soon as I hear from the customer.
    Thanks for your help with this!
    Richard Elmquist
  • Jim,

    The customer asked the following questions in response to your last question:

    It seems customer is feeding Matlab code to DAC then to ADC. When he bypasses the DAC and ADC to check sanity, he directly feeds matlab code to his phase computation software. How is customer ensuring that DAC output itself is not having phase mismatch when its output power increases?

    If there is a phase mismatch in DAC, it is more likely that a constant phase is observed for each different TX patterns loaded (i.e. a single phase differential of 0.6 rads is used all the test cases, and only the amplitude is scaled - all done in Matlab to generate the TX pattern).  On the other hand and if your theory about DAC is correct, we need to look at the DAC characteristic in more detail instead.
    Can you generate a pattern to study this DAC phase offset?  Part number: DAC3162EVM

    Can we help him to generate a pattern that would help him study the offsets or will this simply not work?

    Thanks for your help with this!

    Richard Elmquist

  • Richard,

    Please pass on the test info shown in the attachment.

    Regards,

    Jim

    Phase test.docx

  • Jim,
    Thanks!
    Hopefully this will answer his questions.
    Thanks for your help with this.
    Richard Elmquist
  • Richard,

    Is this still an issue? otherwise, I would like to close this ticket.

    Regards,

    Jim
  • Richard,
    Is this still an issue?
    Regards,
    Jim
  • Richard,

    Is this still an issue?

    Regards,

    Jim