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ADS6442: Test Pattern Out with considerable delay

Part Number: ADS6442

Hello,

After programming the ADC (P/N ADS6442_RGC_64) to pump out specific desired test pattern, I have to wait for 7 rising edges of FRAME signal before the test pattern is fully read out.

This surprised me as I thought that when the pattern is fully pumped out, the FRAME signal toggles from low to high. Thus, only one rising edge in FRAME should have been sufficient. The datasheet doesn't seem to discuss about the FRAME rising edges and test pattern read-out completion.

Is this normal? Is this documented anywhere?

I have the ADC programmed 16-bit, 2-wire interface, DDR bit clock, bit-wise since register 0D is programmed with 1001 0000 101

Thank you very much for reading