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ADS54J60: ADS54J60 LMFC re-align

Part Number: ADS54J60
Other Parts Discussed in Thread: LMK04821

Hi,

does the ADS54J60 converter align LMFC counter only with the first SYSREF event after initialization or re-aligns it on all SYSREF events?

Thank you for your answer

Best regards,

Jiri

  • hi all,

    any feedback?

    thanks a lot in advance

    KR

    Vincenzo

  • some more details about the topic:

    So far, everything worked fine with ADS54J60 converters.

    Next/Last step is to achieve repeatable latency according to the chapter Achieving Repeatable Latency (page 66) in www.xilinx.com/.../pg066-jesd204.pdf.

    Unfortunately it does not works for as expected.
    There is another project with very similar configuration, but with Analog Devices ADC and it works as expected.
    We think the problem may be with ADC LMFC clock.

    The configuration is: 1GSPS, LMFS 8224, K=32 => SYSREF = 1000/4/32/4 = 1.953125MHz

    In other E2E posts is explained that the SYSREF signal must be switched on during ADC configuration. After ADC hw reset is the default frames per multiframe value (K) 10 and because SYSREF is running, LMFC clock is started. Is the LMFC clock automatically re-aligned after change of the K value to 32 in the SPI register? How to re-align it manually?

    KR
    Vincenzo
  • Vincenzo,

    The LMFC is reset on every rising edge of SYSREF. SYSREF is the only way to re-align the ADC after changing the K value. Is SYSREF running continuously in your system? If not, try this.

    Regards,

    Jim   

  • Jim,

    SYSREF is running continuously in our system, we verified it with an oscilloscope.

    Any other idea? Are there any hidden registers for debug/diagnose the SYSREF and LMFC (something as hidden registers for freeze/un-freeze spurs correction circuits)?

    Best regards,

    Jiri

  • 6318.Link Latency in JESD204B devices_TI.pptxJiri,

    How are you actually testing this? Attached is what we did on another device. Is your test setup similar? Have you tried increasing the RBD value and or the K value? In either case, make sure RBD is always = K or less than K. Can you send your ADC register mapping information?

    Regards,

    Jim

     

  • Jim,

    we use a simplified approach to achieving robust repeatable latency from Xilinx (www.xilinx.com/.../67442.html).

    We have a testing firmware which:
    1. Initializes the LMK04821 clock circuit
    2. In the cycle resets the Xilinx JESD204 core, re-initializes the ADS54J60 and reads JESD204 registers

    Value of the BUFFER ADJUST register is very different after every re-initialization.

    For example :
    RX_BUFF_ADJUST_REG0 0x0000000C
    RX_BUFF_ADJUST_REG1 0x0000000C
    RX_BUFF_ADJUST_REG2 0x00000010
    RX_BUFF_ADJUST_REG3 0x0000000C
    RX_BUFF_ADJUST_REG4 0x0000000C
    RX_BUFF_ADJUST_REG5 0x0000000C
    RX_BUFF_ADJUST_REG6 0x0000000C
    RX_BUFF_ADJUST_REG7 0x0000000C

    and after next initialization:
    RX_BUFF_ADJUST_REG0 0x00000000
    RX_BUFF_ADJUST_REG1 0x00000004
    RX_BUFF_ADJUST_REG2 0x00000000
    RX_BUFF_ADJUST_REG3 0x00000004
    RX_BUFF_ADJUST_REG4 0x00000000
    RX_BUFF_ADJUST_REG5 0x00000000
    RX_BUFF_ADJUST_REG6 0x00000000
    RX_BUFF_ADJUST_REG7 0x00000000

    Our ADC registers:
    AdcReg adcreg_init[] =
    {
                    { 0x0000, 0x81 }, // Reset the device
                    { 0x4001, 0x00 }, // clear any unwanted content
                    { 0x4002, 0x00 },
                    //*****************************************************
                    // Main Digital page
                    //*****************************************************
                    { 0x4003, 0x00 }, // page sel
                    { 0x4004, 0x68 }, // page sel
                    { 0x60F7, 0x01 }, // dig reset A
                    { 0x604B, 0x20 }, // format sel enable A
                    { 0x6043, 0x01 }, // offset binary A
                    { 0x6052, 0x00 }, // BUS_REORDER_EN1 disabled
                    { 0x6072, 0x00 }, // BUS_REORDER_EN2 disabled
                    { 0x6000, 0x01 }, // pulse reset A
                    { 0x6000, 0x00 }, // pulse reset A
                    //*****************************************************
                    // Master page
                    //*****************************************************
                    { 0x0011, 0x80 }, // page sel
                    //{ 0x0054, 0x80 }, // manual SYSREF
                    //{ 0x0053, 0x01 }, // SYSREF puls
                    //{ 0x0053, 0x00 },
                    //{ 0x0053, 0x01 }, // SYSREF puls
                    { 0x0059, 0x20 },   // set always write 1 bit
                    //*****************************************************
                    //JESD Analog Page
                    //*****************************************************
                    { 0x4003, 0x00 },  // page sel
                    { 0x4004, 0x6A },  // page sel
                    { 0x6012, 0x02 },  // set always write 1 bit
                    { 0x6016, 0x80 },  // JESD PLL Mode 20X, four lanes per ADC
                    { 0x6017, 0x40 },  // PLL reset
                    { 0x6017, 0x00 },  // PLL reset clear
                    //*****************************************************
                    // JESD Digital page
                    //*****************************************************
                    { 0x4003, 0x00 }, // page sel
                    { 0x4004, 0x69 }, // page sel
                #ifndef ADC_TEST_PATTERN
                    { 0x6000, 0x80 }, // CTRLK
                    { 0x6001, 0x01 }, // 20xmode, four lanes per ADC
                    { 0x6002, 0x00 }, // normal ADC data
                #else
                    { 0x6000, 0x90 }, // CTRLK, Test mode
                    { 0x6001, 0x01 }, // 20xmode, four lanes per ADC
                    { 0x6002, 0x80 }, // 12 octet RPAT jitter pattern
                #endif
                    //{ 0x6007, 0x09 }, // Subclass 1
                    { 0x6016, 0x00 }, // LANE SHARE normal operation (each channel uses one lane)
                    { 0x6031, 0x00 }, // DA_BUS_REORDER
                    { 0x6032, 0x00 }, // DB_BUS_REORDER
                    //*****************************************************
                    //JESD Analog Page
                    //*****************************************************
                    //{ 0x4003, 0x00 },  // page sel
                    //{ 0x4004, 0x6A },  // page sel
                    //{ 0x6012, 0x02 },  // set always write 1 bit
                    //{ 0x6016, 0x00 },  // JESD PLL Mode 20X, four lanes per ADC
                    //{ 0x6017, 0x40 },  // PLL reset
                    //{ 0x6017, 0x00 },  // PLL reset clear
                    //*****************************************************
                    // Main Digital page
                    //*****************************************************
                    //{ 0x4003, 0x00 }, // page sel
                    //{ 0x4004, 0x68 }, // page sel
                        //{ 0x6052, 0x00 }, // BUS_REORDER_EN1 disabled
                    //{ 0x6072, 0x00 }, // BUS_REORDER_EN2 disabled
                    //{ 0x6000, 0x01 }, // pulse reset
                    //{ 0x6000, 0x00 }, // pulse reset
                    //*****************************************************
                    // JESD Digital page
                    //*****************************************************
                    { 0x4003, 0x00 }, // page sel
                    { 0x4004, 0x69 }, // page sel
                    { 0x6006, 0x1F }  // K=32
    };

    We tried to use initialization sequence from the ADS54J60 datasheet (Table 65), but it doesn't work for us. We have to configure the JESD Analog Page and Main Digital page before the JESD Digital page. Do you have any idea why?

    Thank you
    Best regards,
    Jiri

  • Jiri,

    You had a couple of invalid and unnecessary writes in your file. Please try the one attached. Can you explain more about what was shown in your last reply regarding the Xilinx Buffer_adjust registers?  I am guessing these are buffers capturing data from the individual lanes. And ideally the data should be the same on all of these and after doing a system reset? Are you using the ADC in test pattern mode? If so, how is this synchronized with respect to system reset? You must write to these registers to enable this test pattern so there is no guarantee when the data is going to be captured by the Xilinx part at the same time every reset cycle.

    What is the RBD value used by the Xilinx board?

    Regards,

    Jim 

    ADS54J60 registers.docx

  • Jim,

    Can you explain why register writes with its default values are invalid and not only unnecessary? Why your file doesn't respect the initialization sequence from the datasheet (Table 65)?

    All about the Buffer_adjust registers is explained in the article JESD204B - A simplified approach to achieving robust repeatable latencywww.xilinx.com/.../67442.html

    We use the ADC in test pattern mode now. Of course, we don't test its value after the reset, because it isn't defined.

    Best regards,

    Jiri

  • Jiri,

    You can write to all of the registers. I was just removing the ones that you were writing to that you did not have too to save on SPI overhead. There was one register though that needed bits 7-2 to be "0" and you were writing a "1" to bit 7. This was on page 0x6A00 address 0x16.

    I do everything in the Initialization sequence. It is just not in the same exact order. Also, our GUI does the 4-001, 4-002, 4-003, and 4-004 writes with special software commands so I did not list those in the document I sent.

    Do you have SYSREF constantly running?

    What is your RBD value?

    Can you get a valid output tone from your system?

    Are you using the 12 octet RPAT for this test?

    Regards,

    Jim  

  • Jim,

    Sorry, I overlooked wrong value of the register 0x16…

    RBD = K

    We have SYSREF constantly running.

    We get the right output tone.

    We are using 12 octet RPAT test pattern and the output is what we expect.

    Regards,

    Jiri
  • Jiri,

    When I used a narrow pulse input to the ADC and monitor the MSB of the data coming out of the FPGA JESD block, the latency was constant. We are using an Altera Arria 10 FPGA on our capture board. Have you tried something similar? I cannot get the test to work with the test pattern you are using. I am looking into this issue.

    Regards,

    Jim

  • Jim,

    we tried to use the SYNC request through the SYNC REG bit (initialize 0x6900 page 0x6001 register with 0xC1 and set it to 0x41 after some time) and it works as we expected! The BUFFER ADJUST registers have the same value after each initialization. But when we use JESD204 Xilinx core SYNC output for the SYNC requests then the BUFFER ADJUST registers have different values after every initialization. 

    Do you have any explanations for that?

    Regards,

    Jiri

  • Jiri,

    did this solve your problem or do you require any further support?
  • Jiri,
    Are you still having an issue with this? If not, I would like to close out this post.
    Regards,
    Jim