This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC12J2700: SYSREF delay calibration

Part Number: ADC12J2700

We're using an ADC12J2700 with a continuously running SYSREF. To date we've just been using the default RDEL value, but we're seeing some board-to-board (and possible temperature related?) variations where we see the "Dirty capture" get latched.

When we try sweep RDEL to find an optimum value, we seem to get either the "Dirty capture" or the REALIGNED bit set after each transition. In addition, the effects are variable - when changing from RDEL 4 to RDEL 5 (for example) we may see 70% of the changes cause a "Dirty Capture" and the other 30% of transitions cause REALIGNED to be set. From the notes in the data sheet, we were expecting that there would be a range of RDEL values where neither bit is set as we change RDEL.

Questions:

1- Assuming the rest of our design has stable delays, does RDEL need to be calibrated just at the design level? For each individual ADC? Across temperature?

2- Should there be a range of RDEL values where the "Dirty capture" or REALIGNED bits are not set when RDEL changes?

3- Are there any issues with changing RDEL with a free-running SYSREF (not just pulsed once)?

Thanks for any help you can provide

  • Hi Ryan

    Regarding question 1)

    As long as the DEVCLK to SYSREF timing at the ADC inputs is stable across boards we expect that the needed RDEL values will be similar. It is possible that part to part variation in the clock path or ADC input clock delays could be large enough to required a one-time RDEL tuning for each ADC/clocking board.

    Regarding questions 2 and 3)

    I know it is possible to get false REALIGNED flag setting when changing RDEL with SYSREF Processing enabled.

    The best approach when sweeping RDEL values is as follows:

    • Disable SYSREF Processing
    • Set desired RDEL value
    • Clear Capture, Aligned and REALIGNED flags
    • Enable SYSREF Processing
    • Check flag status

    Best regards,

    Jim B

  • We tried implementing this in the lab. We're still seeing some odd behavior. 

    The biggest issue is that we're running into some RDEL values that seem to put the JESD core into a pathological state. When it's in that state, the JESD interface goes down (SYNC is asserted from our FPGA, haven't looked to see if the ADC is putting out K28.5 characters correctly). Once it's in that state, it will stay in that state, regardless of the value of RDEL. Turning the SYSREF processing on and off doesn't have any effect - the only way to clear this is to change to a better RDEL value, and then reset the JESD core (writing 0x3E and 0x3F to register 0x201).

    What we're finding we have to do is:

    1- Change RDEL

    2- Reset the JESD core

    3- Clear the status flags

    4- Check for the Dirty Capture, Realigned, and Sync flags.

    If we do that, we seem to be able to map out the bad offsets.

    We're also seeing that the bad RDEL codes are not stationary - our testing a few days ago had bad results at RDEL=0 and good results with RDEL greater than 0. Today, we're seeing RDEL values in the 2-7 range are bad, but outside that things work well. We intend to run some temperature tests to see how it moves with temperature.

  • Hi Ryan
    I'm glad you've made some progress on this.
    When doing the RDEL sweep you don't need to keep the link active at the receiver. You just need to have the ADC JESD204B TX block enabled and work through the needed RDEL sweep steps, finding the RDEL range where the Dirty Capture flag is set.
    Once the proper RDEL value is determined (away from the range of settings where dirty captures are encountered) and the ADC is configured with that delay value then the link can be enabled at the RX side.
    The only factors that might cause a shift in RDEL values like that would be a change in the timing relationship between CLK and SYSREF, or a large shift in ADC temperature between the 2 cases.
    Let us know the results of the additional testing.
    Best regards,
    Jim B