We're using an ADC12J2700 with a continuously running SYSREF. To date we've just been using the default RDEL value, but we're seeing some board-to-board (and possible temperature related?) variations where we see the "Dirty capture" get latched.
When we try sweep RDEL to find an optimum value, we seem to get either the "Dirty capture" or the REALIGNED bit set after each transition. In addition, the effects are variable - when changing from RDEL 4 to RDEL 5 (for example) we may see 70% of the changes cause a "Dirty Capture" and the other 30% of transitions cause REALIGNED to be set. From the notes in the data sheet, we were expecting that there would be a range of RDEL values where neither bit is set as we change RDEL.
Questions:
1- Assuming the rest of our design has stable delays, does RDEL need to be calibrated just at the design level? For each individual ADC? Across temperature?
2- Should there be a range of RDEL values where the "Dirty capture" or REALIGNED bits are not set when RDEL changes?
3- Are there any issues with changing RDEL with a free-running SYSREF (not just pulsed once)?
Thanks for any help you can provide