DAC37J82: DAC37J82 JESD204B LINK?

8688.DAC37J82_Fs_614.4_K_16.cfgHenry,

I have this setup running in our lab. The config file used is attached. Compare these settings with what the customer is using. We are providing a 614.4MHz clock to the DAC and 307.2MHz clock to the FPGA. When they are getting the errors, have them read registers from address 0x65-0x6C. This will report any errors on the individual lanes. Have them also read address 0x6D to get error status on the serdes  PLL. My guess is they are sending the wrong clock frequency to the DAC or FPGA or both.

Regards,

Jim

Hi JIM

We are still testing the DAC37J82.
Our problem is SERDES PLL is UNLOCK.
The DAC CLK is input at 614.4 MHz. And if SERDES LANE has data, I think SERDES PLL is LOCK.

Set DTEST to 1 or 2 in Config27.
The output value of SERDES BLOCK0 / 1 does not show 38.4Mhz.

What should I review?

DAC37J82 setting.

Serdes Lane Rate : 3072Mbps,
Serdes Rate : QuarterRate,
Serdes PLL=3072Mhz,
Serdes Div=1,
Multiply Factor=5,
Serdes RefClk=614.4M
Serdes Lane : LANE 0,LANE 1
DAC_CLK : 614.4Mhz
Interpolation Factor : 4

DAC37J82 Register Value

Thank you