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ADC digital output unstable (Any design issue?)
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  • Forum Post: ADS807E digital outputs are oscillation only the bit which are high are not effected (Any design issue?)

    shashi kanth
    ADS807E is used in our design, to convert analog input to digital output, expected to work with 50 MHz clock input. We have referred the design used in DEM-ADS807E Evaluation kit (http://www.ti.com/lit/ug/sbau007/sbau007.pdf) Problem faced: When an input signal (reference voltage) is given...
    on Oct 21, 2011

  • Forum Post: Julio Pantoja

    Julio Pantoja
    Hello I am working with an ADC4129 and the TSW1200 EVM borad. This EVM board have a XILINX VIRTEX 4 FPGA. Can I have the verilog code for this TSW1200 EVM? Regards, Julio
    on Jul 31, 2012

  • Forum Post: TSW1200 EVM

    Vaibhav Tripathi
    Hi, I am using the TSW1200EVM to capture the output of an 8 bit 400Msps converter. The inputs to TSW1200 board are provided using the 120pin samtech connector that include 16 LVDS pairs (8 bits) + ADC clock (p and m). I have configured the EVM in single channel SDR format and am using the MATLAB interface...
    on Jul 12, 2012

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