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TI Home » TI E2E Community » Support Forums » Data Converters » High Speed Data Converters » High Speed Data Converters Forum » All Tags » dac5681
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High Speed Data Converters

Welcome to the High Speed Data Converters Section of the TI E2E Support Community. Ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. To post a question, click on the forum tab then "New Post".

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dac5681
  • dac
  • DAC3484
  • DAC3484EVM
  • DAC5681EVM ADS5400EVM Windows7 Software
  • dac5681z
  • DAC5682Z
  • DAC5682zEVM
  • data conversion
  • Fast DAC
  • high-speed
  • initial setup
  • power sequence
  • question
Related Posts
  • Forum Post: DAC5681 or DAC5681Z Power Sequencing

    pjaszkowiak pjaszkowiak
    In the datasheet for the DAC5681Z, there is a note for power sequencing. This note recommends that the 1.8V rails come on simultaneously and that the 3.3V rails do the same afterwards. In my application, it will be very difficult to get these rails timed exactly, so I would like to know how much leeway...
    on Dec 22, 2010
  • Forum Post: Re: Fast DAC converter DAC3484 sampling rate for each channel

    Liang Geng Liang Geng
    Hi Kang, Thank you for your reply. I have been looking into DAC5681 and DAC5682 series. I found that 5682, though dual channel, allow single channel mode. Am I right that saying 5682 in the single channel mode is taking the input data purely to one channel therefore give an 1Gsps conversion just...
    on Nov 17, 2011
  • Forum Post: Fast DAC converter DAC3484 sampling rate for each channel

    Liang Geng Liang Geng
    Hi. I am looking for a fast DAC converter (>1Gsps) for my FPGA based communication system design.Unfortunately after I got the DAC3484EVM, I found this might not fit my application. If I am correct, the DAC3484 has a maximum sample rate of 1.25 Gsps at the digital input end. But for each...
    on Nov 14, 2011
  • Forum Post: DAC5682ZEVM clock and transformer output questions

    Liang Geng Liang Geng
    Hi, I am working on a DE4 board interfacing with DAC5682Z EVM. The requirement of the clkin of the EVM is 1Vrms, what is the most common way of generating this clock? I suppose for the purpose of synchronizing FPGA and DAC, the clock should be generated from the clock network if FPGA? But what...
    on Dec 8, 2011
  • Forum Post: Multiplicative noise in DAC5681 output

    Luis M Brugarolas Luis M Brugarolas
    I am using ADS5681 in a system in which it acts as an Arbitrary Waveform Generator (AWG) with a sampling clock frequency of 312.5 MHz. When characterizing it with sine signals, I have found that the desired sinusoid seems to be modulated by low frequency random noise and various tones. There is nod...
    on Sep 30, 2011
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