High Speed Data Converters

Forum Post: Group Delay Function

Greg Benton — Sat, 25 May 2013 01:50:00 GMT

Where can I find application information on using the "group delay function" for the DAC3484? According to the datasheet:

Sets the group delay function for DACA. The maximum delay ranges from 30ps to 0x00

100ps and is dependent on DAC sample clock. Contact TI for specific application

information.

Thank you.

Forum Post: DAC5675

Stan Vaughn1 — Fri, 24 May 2013 21:10:00 GMT

Hi,

we are testing a DAC5675 development board. We have set up the output for differential with 26 ohm resistors to +3.3V. We are driving the DAC board with a Xilinx SP601 development board and differential LVDS pairs. We have are generating a gaussian wave out of the DAC outputs (approximately 5 usec wide). However, the gaussian wave negative output has an amplitude of 1.0V while the positive amplitude is only 0.6V. What could cause this imbalance?

thanks!

Forum Post: RE: Can JESD204 interface provide deterministic sample time?

Jeffery Pfarr — Fri, 24 May 2013 19:03:00 GMT

Hi Kim,

Please look over the attached .pdf on JESD204 deterministic latency. Alos, please reference http://www.ti.com/lsds/ti/data-converters/high-speed-adc-greater-10msps-jesd204b.page on TI.com.

Forum Post: RE: ADC12D1800RFRB external clock frequency 300MHz

Jim Brinkhurst84999 — Fri, 24 May 2013 18:58:00 GMT

Hi Patrick

The ADC is rated down to 150 MHz input clock frequency, but the FPGA on the board can only capture data down to about 400 MHz.

We have data gathered at lower clock rates during device characterization (using a different capture system).

If you can describe the input signal, operating conditions, and device parameters of interest I can see if we already have data close to what you're looking for.

I hope this is helpful.

Best regards,

Jim B

Forum Post: RE: TSW6011 FPGA

Omar DIOURI — Fri, 24 May 2013 18:46:00 GMT

No, I have not yet contacted the FPGA vendors for this application. so I'll try to configure TSW6011 via the SPI interface and I'll use a block in FPGA SERDES to convert the output of the ADS5282.
thank you

Omar

Forum Post: RE: ADS6145 output data inversed

KW Nam — Fri, 24 May 2013 17:03:00 GMT

Hi, Zaidi

I mean internal pattern as internal test pattern such as ramp or toggle from register 0x0A. Anyhow, it sounds good the issue has gone away.

Thanks,

Forum Post: ADS62P49 Parallel Configuration Only RESET

User42 — Fri, 24 May 2013 16:40:00 GMT

My design has an ADS62P49 that is hardwired to parallel configuration only mode. The RESET pin is tied directly to AVDD(3.3V) as is the SCLK pin. The SDATA pin is tied directly to GND. The SEN pin is tied to GND through a zero ohm resistor.

My question is concerning the internal registers. The datasheet does not specifically state what the internal registers do when using Parallel Configuration Only. The datasheet does state that the internal registers are set to "default" when given a reset either on the reset pin or via the software using the reset bit (bit D7 in register 0x00), but this only applies to serial interface configuration mode. Will the internal registers initialize to their "default" values in Parallel Configuration Only mode and without a reset?

Forum Post: RE: DAC3482EVM configuration issue using EVM GUI (App controls in a "stuck" state)

Pete Harbour — Fri, 24 May 2013 15:33:00 GMT

Kang,

Thanks for your help with this. I have been able to properly configure the following setup:

ADS62P49EVM --> TI_TSW-to-HSMC_bridge --> Altera_S.IV_GX530N_FPGA --> DAC3482EVM

and pass analog signals from end-to-end using the digital loopback function described in the TI writeup "Interfacing Altera FPGAs to ADS4249 and DAC3482". My setup utilizes a DAC3482EVM with a HSMC digital bus connector.

Pete

Forum Post: RE: vhdl source code and .ucf file for vertex 4

Richard Prentice — Fri, 24 May 2013 14:54:00 GMT

Hi,

Take a look at the file extensions in the zip file that got through to the second address and ask your IT if any of them are flagged as potentially malicious. Besides the .v and the .ucf there are a few other file extensions in the zip file that Xilinx uses. Usually I see no trouble with them. If I try to send zip files with .exe or .dll then I often have to change the extension to something like .eexxee to artifically get it past screening for potentially malicious code. But I haven't seen any issues with the file extensions in this zip file before. But some places may also have concerns about zip files in general. Glad you got it finally.

Regards,

Richard P.

Forum Post: DAC3283 FIFO Collision

Naveen Kumar5 — Fri, 24 May 2013 12:29:00 GMT

Hi,

I'm trying to configure dac3283evm with gui, problem i'm facing is FIFO Collisions is enabling. I tried with basic ones given with installer but problem is same..

what could be the reason..

thanks,

Naveen

Forum Post: RE: TSW1400 1400_DAC_Write.vi can't load *.TSW file

gary chen1 — Fri, 24 May 2013 05:56:00 GMT

HI Ken

IT's OK , thinks your help.

Best regards.

Forum Post: RE: Anti Aliase filter between DAC3152EVM and ADS4125EVM

Matt Guibord — Thu, 23 May 2013 15:57:00 GMT

Prashant,

Still I need to have an anti-alasing filter ??
1. Yes, otherwise you will capture the DAC images
If yes, what would be cut-off frquency of that filter as my expected Fin is 5 MHz ?? (May be 5.5 MHz)
1. DAC Fs/2 or ADC Fs/2, whichever is lower.
What if I use a low pass digital filter inside FPGA with same cut-off frequency rather using this low pass anti-aliasing filter before ADC ?
1. Will not work. The DAC images are caused by the digital-to-analog conversion, they cannot be digitally filtered. Review DAC images and ADC aliasing (undersampling).

Regards,
Matt Guibord

Forum Post: RE: Output of DAC3152

Matt Guibord — Thu, 23 May 2013 15:53:00 GMT

Prashant,

You WILL NOT be able to see a DC level at the DAC output if it is coupled through the transformer. The transformer has a center tap, so each DAC output essentially has an inductor to ground. DC current through an inductor will result in 0-V drop across the inductor. Please review the schematic.

Regards,
Matt Guibord

Forum Post: RE: spikes in ads62c17 output data

Matt Guibord — Thu, 23 May 2013 02:58:00 GMT

Hi Donald,

Okay, great! Glad you got it worked out.

Regards,
Matt Guibord

Forum Post: RE: how to set up the DAC348x EVM and TSW1400 PAttern Geenerator

Kang Hsia — Wed, 22 May 2013 20:43:00 GMT

Michael,

Please load the attached register file to the DAC348x GUI for DAC34SH84 operating at 2x interpolation, fs/4 coarse mixer at 1500MHz DACCLK.

The signal you generated from HSDC PRO GUI will be modulated to fs/4 and centered at 375MHz. For instance, if you generated 1MHz tone, the DAC output will be at 1MHz + 375MHz = 376MHz.

Keep in mind the input signal has to be complex signal for the complex coarse mixer to function properly. You can also input negative frequency contents as well, i.e. -1MHz +375MHz = 374MHz at the output.

The input bandwidth is limited by the first stage interpolation roll-off. With 750MSPS of input sample rate, the input bandwidth is approximately 0.4*750=300MHz. For complex modulation, the total input bandwidth is 600MHz.

-KH

Forum Post: RE: DAC3282 EVM with Spartan 6 SP605

Kang Hsia — Wed, 22 May 2013 20:30:00 GMT

Jayme,

The status alarm is the alarm that you need to clear. The masking is used to mask the alarms from triggering the ALARM/SDO pin. Typically in a system, there are two types of alarms: polling and interrupt service routine. The polling process can check the alarms in CONFIG7 at some time interval. However, there may be some critical alarms such as FIFO collision that cannot be missed in between the polling process. Therefore, you will need to unmask the critical alarms so these alarms will trigger the ALARM/SDO pin for the interrupt service routine (ISR).

By default, the Alarm for the ISR is disabled. You will need to enable it for the ISR. For IOpattern checking, you may not need to use the ISR. Polling process would work fine since it is not a critical alarm.

-KH

Forum Post: RE: TSW1400

venkatesh viswanathan1 — Tue, 21 May 2013 18:14:00 GMT

Hi Mat,

1. How long does it take to to download 2 channel of 256K samples each ?

2. How long does it take to upload the same?

3.In the HSDC API doc file the recommended timeout is 30 sec and for firmware download it is more.

Is the timeout ( 30 sec ) here a generic high value or a must have for all functions ?

Above questions are centered around the simulation time.

thanks

Venky

Forum Post: RE: Interfacing Altera FPGAs to ADS4249 and DAC3482

Kang Hsia — Tue, 21 May 2013 14:05:00 GMT

Hi Ouyang,

You may refer to the following forum post:

http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/265659.aspx

-KH

Forum Post: RE: DAC3152 Analog Output Offset Error

Matt Guibord — Mon, 20 May 2013 23:03:00 GMT

Hi,

We do not list min and max values because we do not guarantee the analog output performance. Although most devices should come out close to the typical numbers, there could be parts that deviate from the typical.

Regards,
Matt Guibord

Forum Post: RE: Interfacing ADS4249 and DAC3482 with Altera Statix IV board

Kang Hsia — Mon, 20 May 2013 20:33:00 GMT

Naveen,

For the DAC3482 GUI, there are some example CDCE62005 configuration files that you can use as a starting point. I have attached the files in this forum for your reference. The reference the CDCE62005 synthesizer is the on-board 19.2MHz crystal oscillator. The output of the CDC would be 614.4MHz, 737.28MHz, or 983.04MHz, respectively.

-KH