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ADS5474
Related Posts

  • Forum Post: Data acquisition in the 500MHz range for decay time measurements

    flix
    Hi, I would like to use the ADS5474 14bit/400MHz AD, possibly interleaced, to trace a decay curve. The decay curve will start at a voltage, and then decay typically exponentially to zero. I just ordered the ADS5474 ADX evaluation board - after reading the documentation I think I will be happy with...
    on Nov 5, 2009

  • Forum Post: Switching signals and input conditioning for 1GHz data acquisition

    flix
    Hi, I am dreaming of a system with 2-4 ADS5474 (14bit-400MHz) to measure decay times. To be more flexible, I would like to offer the possibility to either sample 1 channel with (if possible) 1.6 GHz (=400MHz *4), or 4 channels with 400MHz. Do you think, that signal switching with a RF relais, e...
    on Nov 21, 2009

  • Forum Post: ADS5474 EVM question

    PV
    In my set up, I am collecting the data using a Logic analyzer off of the touch less probe connector on the ADS5474 EVM board. The data coming out of the ADC is offset binary and is centered at 2^(N-1) where N = 14 bits. So, I am expecting the center of the sine wave to be at 8192. Instead, the offset...
    on Apr 6, 2010

  • Forum Post: Re: ADS5474 EVM question

    Hui-Qing Liu
    HI, PV Your number shows actually in the device spec. Please see the data sheet spec table and figure 17 for offset error spec. It is the deviation of output code from mid-code when both inputs are tied to common-mode. The offset error is specified as Max/Min = +/- 11mV (+/-82 LSB, about 6 bits) referenced...
    on Apr 8, 2010

  • Forum Post: Re: ADS5474 input impedance vs Frequency

    Hui-Qing Liu
    Hi, It is switched-capacitor ADC. Regards, Qing
    on Apr 27, 2010

  • Forum Post: Re: LVPECL clocking for ADC ADS5474

    Hui-Qing Liu
    Bhupesh, You can use LVPECL clocking the ADS5474 since differential clock amplitude can be down to about 0.5Vpp mentioned in the data sheet. Clock pins has common-mode voltage 2.4v internally biased (mentioned in the data sheet). Yes, you are right to terminate LVPECL driver and use AC coupling between...
    on Sep 3, 2010

  • Forum Post: Re: LVPECL clocking for ADC ADS5474

    Hui-Qing Liu
    Bhupesh, Just wanted to make correction from previous message about the Vcm, the Vcm 3.1v mentioned in the previous answer is for analog input pins (internal biased), the Vcm for clock input pins is 2.4v internal biased (fig 40 in the data sheet). Regards, Qing
    on Sep 3, 2010

  • Forum Post: Re: input configuration using Back to back Balun shown in evaluation module of ADS5474

    Hui-Qing Liu
    Back to back connection on two transformers means the secondary of the 1 st transformer connects to the secondary of the 2 nd transformer, or primary of the 1 st transformer connects to the primary of the 2 nd transformer. The connection between these two transformers is "cross" link. Back...
    on Sep 20, 2010

  • Forum Post: Re: ADS5282 along with FMC-ADC adapter in spartan 6 device

    Eric Seger
    Hello Richard, I will be interfacing the ADS5474EVM and ADS5282EVM to an Altera Cyclone III evaluation board. Please send me the Verilog code for the TSW1200EVM, as that could be a good reference. Send to seger@bridgerphotonics.com. Any other hints/references for interfacing TI ADC's to Altera...
    on Feb 24, 2011

  • Forum Post: Skewed data with TSW1200EVM / ADS5474EVM

    Eric Seger
    Hello, I am trying to evaluate the ADS5474EVM by using a TSW1200EVM to collect the data from the ADS5474EVM. A CDCE62005EVM is the clock source. The ADC clock is 400MHZ and the input waveform is a 10MHZ sinewave. Using the GUI with the TSW1200EVM , it is apparent that the measured data is...
    on Feb 24, 2011

  • Forum Post: Questions regarding ADS5474 and interleaving

    Ro Rus
    Hello, I am looking now at slau247 document: http://www.ti.com/litv/pdf/slau247 where the module interleaving two ADS5474 is shown. I have following questions: 1. Is there any digital tweaking/calibration implemented on Virtex-5 FPGA? Or you just create 800MHz clock in it and register the interleaved...
    on Dec 23, 2011

  • Forum Post: Questions regarding output clock of ADS5474

    Ro Rus
    Hello, Is a DRY output for ADS5474 a free running clock? i.e. not just a data ready output strobe which sometimes might be inactive, and thus making it impossible/unreliable to drive internal PLL of FPGA?
    on Dec 29, 2011

  • Forum Post: RE: ADC12D1800RF - unexpectedly high spur at FS/4

    Stefan Ahlqvist
    To clarify what I mean with the effects of interleaving and the benefits of digital error correction (post-correction) I attach this white paper from one of my colleagues. The results are from a bunch of digitizer products (all of them with interleaved Texas Instruments ADCs, both internally and on a...
    on May 6, 2013

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