High Speed Data Converters

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High Speed Data Converters

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ADS62P43
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Related Posts

  • Forum Post: Re: Interfacing ADS62P43EVM with Vitrex-5 FPGA

    Hui-Qing Liu
    Mahadevan, The first thing we should check is the output data format setting on ADC sided based on the FPGA input data format setting. The ADS62P43 output data including clock output has two formats for both CMOS and DDR LVDS output modes, one is 2’s complement another is straight binary...
    on May 17, 2010

  • Forum Post: Re: Interfacing ADS62P43EVM with Vitrex-5 FPGA

    Hui-Qing Liu
    Mahadevan, Please check if the board is function or not. Please check pin2 at JP15, JP16 for 3.3v, also ADC supply pins for 3.3v, check if the Vcm at clock input pins and analog input pins is in spec. You only need a 5v power supply at P5 for the board. If board looks normal please set the ADC Jumps...
    on May 21, 2010

  • Forum Post: Re: Interfacing ADS62P43EVM with Vitrex-5 FPGA

    Hui-Qing Liu
    Mahadevan, You also can check the device current value, see if it is normal or not based on the spec table in the data sheet. By doing this, you can bypass the LDO and add the supply voltage to the device directly through the jumpers. This way you can find out if the part is damaged or not. Also,...
    on May 27, 2010

  • Forum Post: Re: Interfacing ADS62P43EVM with Vitrex-5 FPGA

    Hui-Qing Liu
    Case Update: Checked the customer borad set up and some measurement through phone, we found the part could be damaged because the source current reading is wrong. The customer is going to get another board and we agreed to close the case. Regards, Hui Qing
    on May 27, 2010

  • Forum Post: Re: ADS62P43 clock inputs

    Hui-Qing Liu
    Hi, Please see the answer under the questions, We have a ADS62P43 and are attempting to interface it with a Xilinx FPGA development board over a 136-pin Samtec connector. Can we drive the ADC clock (CLKP/CLKM) using a differential clock output from the FPGA over a ribbon cable? Yes, at the device...
    on Jul 13, 2010

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