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TI Home » TI E2E Community » Support Forums » Data Converters » High Speed Data Converters » All Tags » ads5400
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High Speed Data Converters

Welcome to the High Speed Data Converters Section of the TI E2E Support Community. Ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. To post a question, click on the forum tab then "New Post".

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ads5400
  • ADC
  • ADS
  • ADS5400 availability
  • ads5400 eval board
  • ADS5400 TSW1200 ADC ini ini-Files
  • ADS5400EVM
  • clocking
  • EVM
  • EVM5400
  • external trigger
  • fft
  • itar
  • ORI
  • overrange
  • over-range
  • parallel ADCs
  • sync
  • time delay
  • TSW1200
Related Posts
  • Forum Post: Re: Availability of the ADS5400?

    Sannatizer35 Sannatizer35
    Hello Michael, The ADS5400 production has moved out as we have waited on another lot to arrive from our FAB. We recently received units and are testing them now. We were hoping to release before the end of the year, but the units for supporting production release at that time had the VCM pin stuck...
    on Mar 4, 2010
  • Forum Post: Re: Availability of the ADS5400?

    Sannatizer35 Sannatizer35
    Hi Michael, I may have been a bit unclear in my response earlier. When I mentioned ' We were hoping to release before the end of the year' this was in reference to the VCM problem material that was to support production at the end of 2009. The material we just received from FAB is being...
    on Mar 5, 2010
  • Forum Post: Master Clock for FPGA on TSW1200 Board

    Mikael Mikael
    Dear Community, I'm dealing with the question, if it's possible to use the Data output Clock from the ADS5400 as the master Clock for an FPGA. How is it done on the TSW1200 Board? I see a crystal on the TSW1200 Board(U10) - is this the Master CLK for the FPGA? I think the FPGA can't...
    on Jun 28, 2010
  • Forum Post: Interfacing ADS5400 with Virtex 6 via a FMC-ADC adapter

    Danh Nguyen Danh Nguyen
    Hi, Can you please describe what are the steps involved for interfacing a TI ADS5400 with parallel LVDS output to the Virtex 6 FPGA via a FMC-ADC adapter? I browsed the forum, and it seems that all the relevant information points to the serial LVDS output from other lines of TI ADC cards. I understand...
    on Jul 27, 2010
  • Forum Post: ADS5400 -Clock Timing Questions

    Jeffery Day Jeffery Day
    I have a number of questions about the ADS5400 adc clock timing. I think I asked them a while ago (many months), but I don't believe I ever got a thorough response, as the parts were still new and being characterized (I believe). If you could help me out with these I'd be very grateful : 1...
    on Sep 29, 2010
  • Wiki Page: The output value of ADS5400 when the input is overranged

    Philip Pratt Philip Pratt
    Q: The output value in the overrange input of ADS5400 by 1369583 Hello, What is the value of output data when the ADS5400 is ±overrange at the input. A: Re: The output value in the overrange input of ADS5400 by 58304 Hi, I checked with the design team today, and the correct answer...
    on Oct 21, 2010
  • Forum Post: interfacing ADS5400EVM and DAC5682ZEVM with altera Stratix IV E development kit

    juli martin juli martin
    hello I am working with altera FPGAs and i need to connect the DAC and ADC evalution modules from texas instruments to the altera Stratix IV E development kit like apears in this link: http://www.ti.com/ww/en/analog/highspeeddataconvertersaltera/ There is any project example in quartus(or some...
    on Dec 2, 2010
  • Forum Post: Re: ADS5400 input

    RJ Hopper RJ Hopper
    Yes, the ADS5400 can sample signals down to DC; however, the ADS5400 EVM is equiped with a transformer that does not pass DC or low frequencies. To utilize the ADS5400 at DC the device will need to be DC couples to the source. --Russell
    on Jan 2, 2011
  • Forum Post: TSW1200 FFT and SFDR analysis problem / question

    Mikael Mikael
    Hi, I've got a question concerning the FFT-function of the TSW1200 software and the SFDR analysis baset on the fft-results. I measured the attached spectrum and see that my highest spurious is HD4 = -70.42 dBc . So i expect that my SFDR value should also be -70.42dBc but the TSW software shows...
    on May 6, 2011
  • Forum Post: Delay in data capture for two ADS5400 with sync'd input clocks and external trigger

    Jon Jon
    Hello, I've been working with the ADS5400 and TSW1200 for a few weeks now and have been struggling to configure two parallel ADS5400 to synchronously capture data based on an input trigger clock pulse. I've been attempting to get the ADS's to capture on the same CLKin pulse, or if...
    on Jul 26, 2011
  • Forum Post: ADS5400 Vcm output drive strength

    Anushavan Atanasian Anushavan Atanasian
    Hi, What is the maximum current rating for the Vcm output? Can it both source and sink current? Thanks
    on Nov 1, 2011
  • Forum Post: Re: ADS5400 Vcm output drive strength

    Anushavan Atanasian Anushavan Atanasian
    Thank you. It would be nice to include this information in the next revision of the datasheet.
    on Nov 7, 2011
  • Forum Post: Specification on ADS5400

    Peter Wan Peter Wan
    Hi Engineers: Can anyone verify the following calculations about the chip ADS5400? The maximum input power level the ADS5400 can handle: The full scale differential peak-to-peak input voltage range for ADS5400 can be down to 1.52Vpp. The differential input impedance can be as high as 115 ohms....
    on May 30, 2012
  • Forum Post: ADS5400EVM Connection to ML605 Board using FMC-ADC-Adapter: Pinout question

    Schuyler Shimanek Schuyler Shimanek
    I am using the ADS5400EVM (Rev D) board to drive a Xilinx ML605 board using an FMC-ADC-Adapter card (Rev C). Is there a constraints file available to map the ADC pins to the FPGA? While creating my own map I noticed that the FMC-ADC-Adapter pins on its J2 connector shown in the Rev C schematic (from...
    on Oct 30, 2012
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