Forums

Hi,

In the earlier posts on the same thread I asked a question regarding the data to be collected from the ADC.

What is the meaning of the following statement in datasheet Page 31 : "The read data command must be sent at least 20 f CLK cycles before the DRDY falling edge or the data are incorrect. Do not the read data command during this time". Is this the update time given on Page 30 in Fig 60?

Your reply to this question was: Yes, you are correct, during this time the internal conversion result register is updated during this time and data is being shifted; therefore, if you send RDATA command less than 20 fclk cycles before DRDY low, the data will be corrupt.  The procedure recommended is to monitor DRDY and send the RDATA command right after DRDY goes low to avoid this situation; or you may always go back to RDATAC mode after configuring the registers. 

However,apart from the grammatical error, dont you think the statement made in the datasheet and your reply contradict each other because the datasheet says that the read data command needs to be issued 20 fclk BEFORE the DRDY bit goes low. You are telling me to issue it after the DRDY bit goes low. I am using stop continuous mode to read data in Pulse conversion.

I have one more query. Sometimes the ADS1259 takes too long to for the DRDY bit to go low after the start of conversion command is sent. Since the firmware has a dependency in ADC conversion, the firmware freezes too. Also sometimes the ADC does not respond for a long time and then suddenly it starts outputting values. Kindly help me out with this problem.Since I do not have more observations on this problem I apologize for not being able to explain the problem in details. PLease ask me any information you need.

Regards

Rahul

Hello Rahul,

The data sheet specifies that new conversion data is available when DRDY goes low. DRDY is an output that indicates when the conversion data is available for reading.  

When the device is running in Gate Control Mode (PULSE BIT =0, default) and the START pin is held high (or a START command is issued) the device starts performing one conversion after another. The data read operation must be completed 20 fclks before the next falling edge of the DRDY.  Therefore, in order to ensure that all data is read in the allowed time; the safest way to perform the read operation is to monitor the falling edge of the DRDY pin, and start the read of conversion data immediately after DRDY goes low. 

On the Pulse Control Mode (Pulse Bit = 1); the device starts a single conversion when either the START pin is set high or when a START command is issued.  The DRDY goes high indicating the conversion has started, and DRDY toggles low when the conversion is completed; and the data is ready to be read.  The conversion results can be read immediately after the DRDY falling edge that indicates the conversion results are ready.

Figure 61 shows STOP continuous mode below.

- On the second question, I am not certain what is causing the DRDY to take too long to go low after the start conversion command is sent.  According to the description, you are using the Stop Continuous Mode and reading data on Pulse Control Mode (Pulse Bit =1).  I have a few questions about your current configuration:

What is the sampling rate used? How long is the time for conversions to happen when the device does not respond?    

I am assuming that START commands are being issued to control conversions.  Is this correct?  If using START commands to control the conversions, is the START pin held low? is Pulse Bit =1?  Are you monitoring the DRDY pin or polling the DRDY bit  in the CONFIG 2 register?

Is the  RESET/PWDWN pin held high? Are you allowing 8 tclk cycles after a RESET high (or 2^16 tclk cycles when exiting a power-down) before communicating to the ADS1259?

Any spikes or noise in the SCLK or RESET lines? The datasheet describes on page 28 that if an unintentional SCLK transition occurs from a noise spike, the device may not respond properly and the port can be reset by either: 1) toggling the CS pin high and then low; 2) holding SCLK low for 2^16 fclk cycles to reset the interface; 3) toggling the RESET pin low and high; or 4) cycling the power supplies. 

If possible,  please send oscilloscope plots of the START, RESET, SCLK, DRDY, DOUT, DIN during a read operation.

Thank you and Best Regards,

Luis

Hi Luis,

On your reply to the 1st question.  I am using 10 SPS, so I should get the DRDY falling edge or DRDY bit in CONFIG2 register goes low every 100 msec.(however I get the DRDY falling edge every 200 msec i.e it takes double the time for all SPS configurations, we can discuss this separately ) after the start command has been issued.I am currently polling the DRDY bit in CONFIG2 register. Hence in the software I will have to send a start command and wait till the DRDY bit is reset which will be 100msec wait time. During this time the processor will not do anything and only keep polling for the DRDY bit which is not acceptable.Another scheme that can be implemented is that the processor gives the start command and proceeds to do other task, and polls the DRDY bit only when it comes to the function block of reading ADC data . But then if the other tasks take more time than required it may happen that the DRDY bit is polled long time after the DRDY bit goes low. Hence the data will be incorrect..Right now my sequence of reading the data is that after i send the start command the state of the READ ADC DATA block is changed and the processor does other tasks and when it comes back to the READ ADC DATA block it checks whether EOC has been received by polling the DRDY bit.If EOC(end of conversion or data ready) is received then it goes ahead with reading the data. In this scheme i have a timeout implemented for DRDY which is of 400msec.Sometimes the DRDY bit gets polled at the wrong time consecutively resulting in a timeout condition This also could be the answer to the 2nd question i asked earlier,although I am not sure about it.  Anyway please can you tell me what is the best scheme to implement to read data from the ADC?

The reset pwdn pin is held high permanently.There is no noise present on the lines now.

Regards

Rahul

Hello Rahul,

If you have a free GPIO available, think it may be easier/more efficient to poll the DRDY pin instead of the DRDY bit; and to control the conversions with the START pin.  

I am assuming you are using the START Pulse mode of operation with the PULSE bit set =1  (is this correct?).  The conversions should be ready after the the programmed "Initial START Delay" has passed and the digital filter has settled. Table 8 shows the DELAY[2:0] registers and corresponding delays in micro seconds.  Also refer to Table 9 (page 24), the conversion times after the START are dependent on the digital filter configuration.  For example, the conversion data is ready after 200ms when the device is set to 10SPS with fclk = 7.3728MHz, SINC2 filter and a Delay[2:0]=000  

If you are controlling the conversions with the START pin (or command), the user should be able to read the results before sending the next START pulse to commence a new conversion.  The other issue to consider is to not to toggle the START pin during a conversion.

After setting the configuration registers; are you able to read the conversion registers without issues? can you please confirm the configuration registers? What filter configuration is being used?

Are you using the START pin to pulse the conversions or the START command? Please provide oscilloscope plots showing the CS, SCLK, DOUT, DIN, DRDY, START during a read conversion operation and a write Register operation.

If possible, please provide an schematic showing the ADS1259-PGA280?

Thank you,

Best Regards,

Luis