I am converting an existing implementation to an ADS8332. I am having some issue so I came to the forum. I noticed in another post, SDI waveforms with the opposite polarity than what my earlier ADC used. For the ADS8332 is the SDI signal nominally low going high, or nominally high going low? --- Thanks in advance. --- Leonard
The ADS8332's focus is on the falling edge. So, if CPOL = 0, then CPHA = 1 (since phase 1 would be the second active edge => First falling edge). If CPOL = 1, then CPHA = 0 (since phase 0 would mean first active edge => First falling edge). [Also important to note that /CS must toggle]
Michael, thanks. I am working with a 5409 and do not see anything in the 5409/ADS8332 literature that references both CPOL & CPHA (except one mention in SBAS363B that CPOL=1 and CPHA=0). The serial link "appears" to work, but my results are oxFFFF for all channels (except for the lsb). That leads me to believe that the ADS8332 is not reading my analog input channel selection. I drop /CS to read and write. I've tried write then read, and read then write ... no difference. I am going through the ADS8332EVM to get to the ADC. Any suggestions? --- Leonard.
Finding the critical edge for this device may be a little tricky. In this particular interface, the SDO data bits do not change on a specified clock edge but, instead, a fixed time after the falling edge (tD1, tD2 timing specs). Therefore, depending on the speed of your SCLK and the data setup and hold times for your microcontroller or FPGA, you could read back data on either the rising edge or falling edge of SCLK without a problem. Latching data into the converter (SDI) is done on the falling edge of SCLK and you can see this looking at the tSU4 and tH3 timing specs in the timing diagrams section of the data sheet.
Hope that helps,
Thanks Tony for helping to clerify!
Also, assuming by '5409' you mean TMS320VC5409 DSP, you'll want to follow Figure 5-23 or 5-26.
Thanks. I may not have a document that I need. It is a TMS320VC5409, but I do not find a Figure 5-23 or 5-26 in any of my literature. What document is that?
Sorry. I had it. SPRS082F.
The literature that I'm looking at is the latest from the product folder [SPRS082F, Revised October 2008]
Figure 5-23 is on page 74, and 5-26 is on page 77.
No joy yet. Please give me some insight into these:
1. Is it necessary that I issue a "Read Data" (0xD000) to get meaningful traffic from the ADS8332? For example, after every channel select?
2.Under what conditions should SDO display voltage levels rather than a serial stream?
The basic cycle (1-5) from which I am trying to get meaningful results is:
0. My “Write CFR” is 0xE0FF.
1. Lower FS/!CS
2. Issue a "Select analog input channel" command
3. Wait for transmit buffer empty
4. Read data
5. Raise FS/!CS
FS/!CS is almost a square wave on 3.3us
I properly decode the "Select analog input channel" on SDI.
I measure the inputs to the ADS8332 and see that all of the channels are 0V except two that I have set to be 1.88V and 2.6V.
The scope shows SDO goes high after FS/!CSß0 for about 1us.
Can you tell from this what I am doing wrong?
First off, double check that you are having SDI input data change on the rising edge of SCLK so that it is valid when it is latched on the falling edge of SCLK.
Second, what voltage do you have on each specific channel?
Third, it looks like you are planning to use the part in manual channel mode with auto trigger. The ADS8331/ADS8332 supports 3 of the 4 possible configurations of channel
select mode and start conversion mode. Auto, channel select mode with
Auto-trigger mode is supported, Auto-channel select mode with Manual-trigger
mode is supported, and Manual-channel select mode with Manual-trigger mode is
supported. Manual-channel select mode with Auto-trigger mode is not supported.
The reason being, in Auto-trigger mode their is not control over /CONVST to EOC
timing causing you to violate the timing specs when attempting to change the
channel in manual channel mode. If run in Manual-channel select mode with
Auto-trigger mode, the ADC will will continuously output the converted data for
However, there is a "work-around" way to change channels and get
the ADC to work in Man-channel select mode and Auto-trigger. To run it in this
mode and change channels follow the steps below:
- Power on the ADC and set the CFR accordingly for Auto-trigger and
Manual-channel select. You can perform a read back of the register is verify
that you are communicating with the ADC correctly and set it correctly.
- Check the output of the ADC, you should reading back the converted data
from channel zero.
- If you want to change to read channel one - Write to the CFR to set the
ADC to Manual-trigger mode.
- Write to the ADC to set the internal mux to channel one.
- Write to the CFR to set the ADC back to Auto-trigger mode.
- Now your output will read back the converted data for channel one. You can
repeat this process to read back any of the channels in auto-trigger,
manual-channel select mode.
As of right now I do not know if we plan to write this procedure into the
data sheet. I know we plan to revise the data sheet to make it clear that
auto-trigger, manual-channel select mode is a supported mode in the ADC.
However, if you follow the procedure above you can get it working.
Thanks Tony. I tried it and it appears to work; however, the added communications eats up my processor time. I will use one of the supported modes. Thanks again.
I am still wrestling with this. After your last post, I beefed up my initialization to read back the CFR. With some rigging I got it to give me a valid feedback one time, but that was all. After looking at my waveforms, and comparing them with another post ("ADS8332 stops EOC operation in Auto channel sel mode"), I see issues, but have not been able to resolve them. I have attached a JPG of my waveforms (at this point I have ignored that I have not properly communicated with the ADS8332 so that I can see McBSP working). The TMS320VC5409 is master (CLKSTP=10, CLKXP=1, and others per Table 2-31, SPRU302) .
Help! Does it look like I have a sick part?
Do you have the ability of disconnecting your SCLK line from the ADC to see if the issue is the SCLK pin from the ADC is fighting to pull the SCLK line low or if there is something else going on? Does this always happen or just happen once you changed your SCLK to idle high?
I received your email and response. I had tried your procedure mentioned. It's ok when hardware only link to IN1 and set Auto-trigger and Manual channel select mode. I measured waveform of IN1 and MUXOUT on chip ADS8331. It's ok and AD value also be ok.
So I want to confirm some point:
1. If hardware only use one channel, it should be better to link signal to IN0, right ? It's easier to initialize Auto-Trigger and Manual channel select mode , and send CFR 0x0000 to select channel zero. Because channel zero is the default channel in this mode.
2. Because i want to use 500kSPS, so i must select Auto-Trigger mode , right?
3. ADS8331 datasheet not mentioned this procedure in latest version, when will you plan to upgrade datasheet? Maybe there will be some users meet the same issue as mine if they just has one channel and link to IN1/2/3 ,and use Auto_Trigger and Manual channel select mode.
Thank you for your help. And hope your response ASAP. ^_^
1. If you decide you want to only use one channel with auto trigger mode, channel 0 would be best. If you want to use a different channel for the single channel, you need to put the ADC in manual trigger mode to switch the mux. After the mux is switched, you can put the ADC back into auto-trigger mode to begin conversions. See the comment under Table 1 on page 22 of the data sheet.
2. Not a must. You can use the /CONVST pin to control the data rate timings. Pulsing the pin every 500kSPS would achieve the same data rate as using auto-trigger mode.
3. It was just recently added a month or two ago. It was added under Table 1 on page 22 of the data sheet. The e2e post discusses the work around procedure in some more detail.
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