Hi, I am using ADS1148 in my design for data acquisition applications with 3-wire RTD - PT100 sensors.For better result I am using both the current sources (IDACs), available on-chip. Operating range of temperature is -40degC to +70degC. For error estimation, I am considering initial mismatch in IDACs, which is specified as typ +/-0.03% of FS in datasheet. Also there is Temperature drift matching parameter, which is specified as typ 10ppm/degC. So, could you please clarify on followings: #1. How should I consider the overall effect of IDACs' initial mismatch as well as temp. drift matching between IDACs for the error estimation? #2. If I refer to IDAC DRIFT curve provided in the datasheet (please refer to figure13 on page no.14), it seems that maximum IDAC mismatch is 0.004uA at 1.5mA IDAC setting. This comes to (0.004uA*100/1500uA) = 0.000267% of FS, which is very very less compared to the specified mismatch as typ +/-0.03% of FS. So could you please clarify that which data should be considered? #3. It will be of great help if you could specify the Total Unadjusted Error(TUE) for the ADS1148. Thanks and regards, Rajesh Kumar
Hi Rajesh,
The reference inputs of the ADS1248 are relatively high impedance with a typical bias current of ~30nA. For the ADS1248, you probably will need a capacitor accross the REFN and REFP. If the other ADC is also an ADS1248, you will probably just need another capacitor in close proximity to the REFP and REFN of the device. Depending on how much current your other DC shifting circuitry consumes, you may need a buffer. If you are feeding the REF5025 into the positive input of the OP-AMP of the current to voltage converter; this is also a high impedance point and the REF5025 should be able to drive it.
If you could please post your schematic, we will be happy to review it and this will help us avoid any confusion.
Thank you and Best Regards,
Luis
Hi Luis,
I hope everything is fine.
Now I am back with couple of queries regarding input signal filtering:
As you know, one channel of ADS1248 is connected to RTD input and other channel is used to measure mA input current. I have ADS1248 evaluation board sch
with me. In this sch signals are filtered using RC LPF prior to the ADC. As I calculated the common mode and differential mode cutoff frequencies, these are
72MHz and 16.9KHz respectively. I have used following formula
Now suppose in my design ADS1248 is configured for 20SPS, so this means modulator frequency is 32KHz(please refer to Table 8 of the datasheet). Considering this signal BW should be limited to16KHZ i.e. half of the sampling frequency. So having said all these could you clarify on the following:
1. Why there is a large difference between these two cutoff frequencies? On what factors, these two frequencies depend? Basically I want to know how do we select these two cutoff frequencies? Also, are there any constraint while selecting these passive components values, such as tolerance and TC(ppm)?
2. As I told you that other channel of ADS1248 is used to measure mA current using a shunt resistor, say 100 ohm. This voltage is fed to the ADC through an in-amp. Here, can I use the same RC filtering for this channel also? Or different filtering is required? Could you comment on this.
I am awaiting for your valuable inputs, Luis.
Best regards,
Rajesh
I hope you had a long Ester holiday and restful weekend.
Could you please clarify my queries regarding LP filtering mentioned in previous mail...I need to finalise the design quickly.
Rajesh,
The more important filter is the differential. If you add a common mode filter, the common mode caps must be 1/10th the size of the differential caps to limit any affects of drift due to mismatch of the common mode filters. The same problem can also be seen if you only use common mode filtering. Any initial mismatch, or mismatch due to drift will cause a differential voltage to be applied at the inputs. In the case of the 3-wire RTD, you need to make sure the resistors are well matched as there can be a difference in potential as current flows through them creating an error. So you design the filter so that the differential filter is an anti-aliasing filter for the modulator rate. Sometimes the anti-aliasing filter is not adequate depending on the input signal and digital filter of the device and a higher order filter (active) is necessary. In your case the simple RC should be sufficient. In general, any component in the analog signal path should be of the best grade you can afford to limit any effects of drift. Another consideration in particular is the grade of cap used. The caps also have a voltage coefficient, so they can change characteristics depending on the applied voltage. Noise is also a consideration. The filter caps should be C0G/NPO or better (Poly or Silver Mica) for best overall performance.
For the INA you can use the same filter if it is adequate for anti-aliasing. The INA will have a particular operational BW and as long as the anti-aliasing filter is adequate to limit any higher frequency content from aliasing back you should be ok.
Bob B