Hello,
I am trying to convert a single sided signal into differential signal and use ADS8363 (EVM) to sample. My signal is 0-5v range but after the ADC I get only half range signal.
I7455.SCAN0001.PDF have attached a pdf file showing my connections.
What am I missing?
Thank you.
Basu
Hi Basavaraj,
Lets start by looking at the full scale input range of the ADS8363 (+/- VREF), in your case +/- 2.5V. The circuit you have around the THS4131 right now will differentially create a 5V signal on the input of the ADS8363 when VS swings to 5V. You could change VREF to 5V to fix this, but you would still only be operating over half the range of the ADS8363.
To utilize the entire range of the ADS8363 we need to look at the circuit you have around the THS4131. Right now you have the negative terminal at ground and your 0-5V signal on the positive terminal. This is always going to yield an output that swings from 0-5V differentially - see the simulation below for clarification:
If, instead, you apply 2.5V at the negative terminal of the op amp we get an output that does swing positive and negative (differentially) that should work with a 2.5V reference on the ADS8363, in fact this configuration will maximally utilize the resolution of the ADS8363. See below:
This should fix your problem.
Edit: Modified the simulation axis to make this more clear
-------------------------------------- Kevin Duke Precision DAC Applications
Hi Kevin,
I like your solution. I had thought of using a 5V reference as well but the ADS8363 only takes 0.5V to 2.525V reference. I might also suggest just using a single-ended input and bypassing the THS4131 altogether (buffering the signal if necessary):
This is also a +/-2.5V signal, when referenced to 2.5V.
Regards,Chris
Christopher Hall | Δ-Σ Data Converter ApplicationsTI.com | Selection Guide | Technical Documents | Tools & Software | Design Notes | E2E Site Map
Christopher HallI had thought of using a 5V reference as well but the ADS8363 only takes 0.5V to 2.525V reference.
A fair catch! I fell victim to just checking the ABS MAX table.
Should this scheme be implemented I would be carefully aware of buffering architectures on the reference voltage/negative input. Since this is a SAR and the input impedance on the negative terminal is non-static I could see potential impact on the reference voltage depending on the drive strength of the buffering amplifier from the reference source. It may be no concern, but I have not tried such a configuration before.
Hello Kevin and Christopher,
Thank you for the replies. We have tried Christopher's solution and it works. But we would like to have the buffer between ADC and our system. We will try Kevin's solution and update you guys.
Thank you again.
Best Regards,
Hello Kevin and Chritopher,
This solution (shown in simulation figures) seems to work. But I have my signal connected to the positive input not to the negative input as shown in the simulation. Am I missing something here? There is also a shift 300mv in the peak signal value. May be this is coming of resistors (1% resistors used)?
Basavaraj,
Can you deliver a scope capture of this drift? Additionally, how are you deriving the voltages to drive the Vocm and the negative terminal? Maybe probe these voltages as well to ensure that they are where you expect and not drifting. If you're using 1% resistors and the values in the simulation I don't think you could get a shift of such magnitude...more like ~50mV.
I am using voltage divider for both. I will switch to 2.5v regulators and see if that helps.
I will try to get some scope captures tomorrow.
When you post your scope captures please also include a complete schematic for the relevant sections of your design for this problem. I'd like to assume as little as possible so we can get your problem solved quickly!
Hello Kevin,
We have the amplifier and ADC working. It needed a clean 2.5v reference and we were not providing it earlier. After we used a 2.5V regulator, we are getting a much better signal.
Thanks for all the help.
Happy to help, let us know if anything else comes up.