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Thanks Tom, I didn't even think of looking at the reference design because reference usually doesn't mean a board!

Tom,

Another question on power:

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We have a major power consumption issue (ADS1672) that we need to resolve before looking at the ADS1675.  I will assume the same answers apply to ADS1675. 

Data sheet shows 3 power numbers:

Power down = 5mW

TYP power dissipation = 350mW

Max power dissipation = 370mW

Question – How much does the power vary if there is no conversion in process?  I.e. start is inactive.

Question – Can you break down the power numbers more so that I know what area of the chip consumes it?  Example – modulator, filters – LVDS interface.

Question – Any suggestion on power saving?

Hi Terry,

I don't have the exact breakdown but the delta in power consumption from 'start' being active to inactive will be minimal - the bulk of the power is consumed by the modulators and bias circuitry.  The LVDS interface is only a minor portion of the overall power consumption.  I'll look through the design documentation and see if I get get you some real numbers.

Thanks Tom.

Terry

Another question on this:

I am trying to figure out how much time, at the system level, I need if I enter and exit power down mode. 

For now, looking at 1672, I see the following in your data sheet:

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When not in use, the ADS1272 can be powered down by taking PDWN pin low. All circuitry shuts down, including the voltage reference. To minimize the digital current during power down, stop the clock signal supplied to the CLK input. Make sure to allow time for the reference to start up after exiting power-down mode.

After the reference has stabilized, allow for the modulator and digital filter to settle before retrieving data.

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I am trying to calculate the required exit time from Power down. 

Q1 - What is Time for voltage reference to stabilize?

Q2 - What is Time for modulator and digital filter to settle before retrieving data?

I do see settle time data after each data is retrieved depending on the filter configuration.  But I do not see any timing exiting PWR-DWN

Hi Terry,

Unfortunately I can't give you an absolute answer for Q1 - the reference stabilization is going to be dependent on the external capacitor you have on your board as well as your layout to some extent (parasitic capacitance, etc).   I'll look into Q2 for you and see what I can find out.

Hi Tom,

My name is Magid Fazel from Teledyne RDI.  I am the customer who was asking all of these questions from Terry.  Terry suggested to contact you directly. 

Thanks for the follow-up.  I wait for the response to the second question.  Meanwhile, I am confused about the reference stabilization comments and the capacitors. Is the “reference voltage stabilization” time referring to the time for our board to make sure the voltage reference is stable?  If so, why does it depend on the power down signal going to the ADS device?  Perhaps, you can provide details on your own reference board.  Are you referring to the capacitors C23 and C24 in your reference design? 

The statement in the data sheet gave me the impression that part of the reference voltage is internal to ADS device.  Please assume that we do NOT turn off the reference voltage or any or the power rails when we go in power down.  Assume that we assert the power down to the ADS device AND turn off the 20MHz to the ADS device ONLY.        

I am basically trying to put the device into power down state in between accesses.  I need to know how much time I need to allocate to the ADS device going into power down and coming out of power down.  I am obviously controlling the external power, reference voltage, clocks to the ADS device.  All I need to know is how long will the device require.

Thank you very much

Magid

Hi Magid,

I'll be in touch with you soon to discuss details.