I posted this issue quitre a while ago, but with partial test.
Now I have to do full test and found very disappointed response from the device, it gives me totally wrong results, the readings are way different than the input
VREF is tied to 4096 mV for 12-bit ADC, so the read result is supposed to follow the input
My procedure is
I tried to read resulst by 2 ways
1) Using 2 separate operations (each has its own SPI CS)
1a) Write 4 bits of channel number 0 or 1
1b) Write 4 bits of 0xD and read 12 bits of result
2) Using only 1 operation (one SPI CS) with writing first 4 bits of channel number and read 12 bits for result
Both ways give me the same resuls as in the table above
What's wrong with me in reading results ?
Below is a capture of its circuitry
The capture that you provided for the circuitry of the ADS7230 is not visible for some reason on your post, can please attach another copy of it so that I may reveiw how you are driving the converter? I would also like to see what kind of LPF you have on the front end of the device as this may add to some of your troubles.
Also, can you please provide me with a scope capture of your DOUT, SCLK, and FS/CS so that we may verify that you are reading off the right critical edge for this part? From reveiwing the data sheet (page 13, Figure 3. Timing for Conversion and Acquisition Cycles for Autotrigger (Read While Converting)) it appears that while operating in the auto trigger mode that the critical edge would be the falling edge of the FS/CS. Is this how you are operating?
Attached is PDF file with waveform capture in writing and reading CFR with config data 0x4FD and circuitry of the chip
8686.ADC ADS7230 Test Results 02.pdf
Take a look at this post -
I am fairly certain that the ADS7230 shares the same digital core as the ADS8332 so the same operating conditions hold true. I would trying either using auto trigger auto channel mode or manual trigger manual channel mode to see if you start seeing the correct results.
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