i have modified my GET_ADC_DATA function now iam getting value for single channel , channel zero ,how to read adc value for second channel, Please help here is my code
1)I have enabled TAG bit ,i never get TAG BIT=1 , I always get TAGBIT=0;
2)I configure cfr with bit pattern but when i read CFR register it not gives same pattern as write. ,I always get D0=0 system reset .
3)my adc data for CH0 is not proportional to the input applied .
I AM ATTACHING SCOPE SCREENS IN DIFFERENT POST BECAUSE IAM ANBLE TO ATTACH IN SAME POST.
CFR DATA WRITE AND READ
my code
void ads8328_ini(void) //CONFIGURE CFR { seventeenth_clk=0 ; GPIO_WriteBit(SPI_CLK_PORT, SPI_CLK_PIN,(BitAction)0); GPIO_WriteBit(ADC_STRT_PORT,ADC_STRT_PIN,(BitAction) 0); GPIO_WriteBit(SPI_NSS_PORT,SPI_NSS_PIN,(BitAction) 0); ADC_CONFIG =0xE8FF ; WRITE_ADC8328(ADC_CONFIG) ; //WRITE CFR SPI1_Buffer_Rx[4]=GET_DATA_INT ; GPIO_WriteBit(SPI_NSS_PORT,SPI_NSS_PIN,(BitAction) 1) ; ///////////////////////////////////////////////////////////////////////////////////// delay_us(10); GPIO_WriteBit(SPI_NSS_PORT,SPI_NSS_PIN,(BitAction) 0) ; WRITE_ADC8328(READ_CFR) ; //READ CFR SPI1_Buffer_Rx[5]=GET_DATA_INT ; GPIO_WriteBit(SPI_NSS_PORT,SPI_NSS_PIN,(BitAction) 1) ; delay_us(10); // select_ch0(); }//////////////////////////////////////////////////////////////////////////////void adc_read_ch_auto(void) { seventeenth_clk=1 ; GPIO_WriteBit(ADC_STRT_PORT,ADC_STRT_PIN,(BitAction) 1) ; //start 1 GPIO_WriteBit(SPI_NSS_PORT,SPI_NSS_PIN,(BitAction) 1) ; //nss1 temp_bit=1 ; //while(temp_bit==1) //check EOC pin status temp_bit = GPIO_ReadInputDataBit(ADC_EOC_PORT, ADC_EOC_PIN) ; delay_us(1);//20ns GPIO_WriteBit(SPI_NSS_PORT,SPI_NSS_PIN,(BitAction) 0) ; //nss0 WRITE_ADC8328(READ_DATA) ; //READ CH0 DATA if(TAG_BIT == 0) //TAG BIT=0 ; { SPI1_Buffer_Rx[0] = GET_DATA_INT ; } else if(TAG_BIT == 1) //TAG BIT=1 ; //READ CH1 DATA { SPI1_Buffer_Rx[1] = GET_DATA_INT ; }
Hi Ram,
You are not reading the CFR properly. MOSI and MISO are both valid on the falling SCLK edge and it seems as though you are using the rising clock edge to try and read back the CFR - your read is correct if you shift everything (0x11FE >>1 is 0x08FF). Your SCLK speed is roughly 40kHz, so the SDO from the ADS8328 is going to look like it should be read on the rising clock, but if you zoom in very close, you will see that you have at least td(SCLKF-SDOINVALID) time to read the output data. At full speed on the SCLK, the output data will look like it has the same clock phase relationship as the input data has.
When configured for Auto Trigger, you have to be able to read data from the ADS8328 at its maximum speed (500KSPS). By your scope_5 picture, it seems as though you are reading at ~1.4kSPS - that is why your EOC looks somewhat erratic - you are actually reading in-between sample/conversion cycles. If you cannot speed up your processor to the point where you can sustain 500KSPS, you'll have to use the part in Manual Trigger mode.
Regards,
Tom