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DAC7578 Questions

This question is answered
Justin Payne
Posted by Justin Payne
on Apr 11 2012 11:19 AM
Prodigy10 points

Hi, I'm creating a design around the DAC7578 QFN-24 package, using it to supply low-current voltages between 0-+5V, and had some questions I couldn't answer with the data sheet.

I'm more or less uninterested in using the CLR pin, can I let it float? Or do I need to connect it to +5V to prevent unwanted hardware resets?

Can I supply both AVdd and Vref with the same regulated +5V rail? What is the behavior if Vref and AVdd aren't supplied at the same voltage?

I'd appreciate any info. Thanks!

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  • Christopher Hall
    Posted by Christopher Hall
    on Apr 11 2012 13:48 PM
    Verified Answer
    Verified by Tom Hendrick
    Expert6750 points

    Hi Justin,

    Welcome to the TI E2E Community!

    I would recommend pulling up the CLR pin on the DAC7578 if you don't plan to use it, just to avoid potential issues.

    AVdd and Vref can be supplied from the same regulated +5V rail. This supply rail should be clean since any supply ripple will directly impact the DAC output voltage. You should have bypass capacitors placed close to the DAC AVDD and Vref_in pins (See the layout section on page 45 of the DAC7578 datasheet).

    Vref may also be supplied by another reference voltage source lower than the supply rail. Changing Vref changes the full-scale output of the DAC as seen in equation 1 of the datasheet..

    Regards,
    Chris


    Christopher Hall | Δ-Σ Data Converter Applications
    TI.com | Selection Guide | Technical Documents | Tools & Software | Design Notes | E2E Site Map

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  • Christopher Hall
    Posted by Christopher Hall
    on Apr 11 2012 15:48 PM
    Expert6750 points

    Justin,

    One more note about using Avdd and Vref on the same rail which is not plainly shown in the datasheet:

    You'll notice the resistor string output of Figure 112 goes to an Output Amplifier (shown below). This amplifier is powered from the Avdd supply rail and, like all op amps, inherently has some output voltage swing limitation. This affects the DAC's output, only allowing the maximum output to go within 10's of mV from Avdd. Therefore, if your output needs to go all the way to 5V a slightly higher Avdd must be applied.

    I hope this information has been helpful for your design!

    Best regards,
    Chris


    Christopher Hall | Δ-Σ Data Converter Applications
    TI.com | Selection Guide | Technical Documents | Tools & Software | Design Notes | E2E Site Map

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  • Mark Gill
    Posted by Mark Gill
    on Apr 08 2013 15:23 PM
    Prodigy90 points

    Hi Chris,

    Might I start off by saying thanks for all the support! Onto business:

    You have referenced page 27 of the datasheet here, saying that Vrefin can only reach 5V.

    I also see on the datasheet on page 2 that Vrefin can range from -0.3 to AVdd + 0.3, where AVdd can be as much as 6V.

    Does this mean if Vrefin is greater than 5V, the DAC will register Vrefin as 5V?

    DAC reference voltage
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  • Christopher Hall
    Posted by Christopher Hall
    on Apr 08 2013 15:51 PM
    Expert6750 points

    Hi Mark,

    You can use a reference voltage slightly higher than 5V and that will bias the resistor divider string of the DACx578.

    The table on page 2 of the datasheet is the absolute maximum ratings of the device. Exceeding those values can potentially damage the IC, so it is best practice not to operate the device at those limits. The "AVdd + 0.3" upper limit on the reference voltage tells me that there is an ESD diode connection between Vref and AVdd, so operating Vref higher than AVdd is forward biasing an ESD diode and would sink additional current from the reference source.

    Regards,
    Chris


    Christopher Hall | Δ-Σ Data Converter Applications
    TI.com | Selection Guide | Technical Documents | Tools & Software | Design Notes | E2E Site Map

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  • Mark Gill
    Posted by Mark Gill
    on May 29 2013 10:17 AM
    Prodigy90 points

    Hi Chris,

    Sorry for the late reply. Your post has been very helpful. 

    Best,

    Mark

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