Dear TI Community,
I'm over a design using the octal DAC DAC8718. The status quo is:
- The DAC is on a homebrewed double sided PCB completeley separated from the other digital circuit stuff
- This board is connected to the digital board using two iCoupler digital isolator chips sitting on a 3rd PCB
- The boards are connected with each other using 10 wire flat ribbon cables (length: approx. 10cm = 4")
- Supply voltages come out of two separate laboratory DC power supplys. One for the µC and other digital stuff as well as the µC side of the iCoupler isolator board, the other one supplies the DAC board as well as the DAC side of the iCoupler isolator board. The two power supplies don't have any ground or other connection with each other.
- I installed 33 ohms series resistors into the following lines: SCLK, SDI, \CS, \LDAC, SDO. Unfortunateley I didn't install them onto the DAC board, but onto the isolator board, so quite far away from the bus endpoint
- The configuration of the DAC is as follows: AVDD=+15V, AVSS=-15V, DVDD=IOVDD=3.3V, Vref=1.25V (REF3212), Gain = 6
- Supply Pins are decoupled as follows: 10µF||100n@AVDD&AVSS, 1µF||100n @DVDD&IOVDD, 100nF@REF-A&REF-B
- The DAC board uses split AGND and DGND ground planes connected near the DAC (<1cm=0.4")
Here's the schematic of the DAC Board:
Figure 1: Schematic of the DAC board (click to enlarge)
OK, that are the priors, now the problems.
1. I have - in my opinion quite serious - SPI interference in my DAC output signal. Figures 2 to 4 illustrate this. See figure descriptions for further details. Can anybody please tell me what to do to get rid of this? Has anybody reached better performance?
Figure 2: What you see is DACOUT3 as well as some digital control signals as descripted in the figure. DAC3 is performing a -16LSB step on the 4th rising edge of \CS. The code transition is from 0x7FC0 to 0x7FB0, which is near midscale (0V). As you can see, the DACOUT3 signal is quite serious corrupted by the SPI communication signals. Most prominent one is SCLK but also the \LDAC spike (which is currently not used but inserted for demonstration purposes) causes a spike in the output signal.
Figure 3: This is just a zoomed version of Figure 1 which shows clearly the relationship between the SPI signals and the 'noise' at the output.
Figure 4: Another more zoomed version shows that the \CS signal causes an interference at the output, too.
Any suggestions for removing these spikes? I took care to route any high speed digital signal within the DGND plane. Supply cables are about 15cm = 6" in length. The output signals are measured with the probe connected directly to the pin header which is about 2.5cm = 1" away from the DAC. No load is connected to the DAC.
@TI staff: In the datasheet (all traces on p.24) I cannot see anything, which looks like SPI interference. You use a load consisting of 10kohms||240pF. If I do this the circuit begins to ring. Maybe you can test the circuit without any load and tell me about your results.
Ok, enough about SPI interference, let's come to the second problem, the settling time. In the datasheet (p.24) the DAC settles in about 14µs to less than 1LSB as a response on a full scale step and within about 10µs on a half scale step. Now have a look at my records (Figure 4 and 5)
Figure 5: This is a step of about -55mV which corresponds to a codestep of -480LSB. After the trigger (rising edge of \CS) the output settles down -3.5mV within 242µs. 1LSB is about 115µV. It looks like an exponential decay.
Figure 6: This is a step of about -275mV which corresponds to about -2400LSB (5x-480LSB). The decay is similar in duration but higher in amplitude. Seems to depend on the step amplitude.
By the way: You can see the SPI interference again in both figures, 5 and 6.
Hopefully anybody has an idea of solving any of these two problems. Both would be even better. Maybe there is even only one solution for both problems which would be the best case for me ;-). If you have further questions about the setup, don't hesitate to ask.
You have a lot of questions here so let me try to address some of them and then we can go from there. The schematic you posted I have some concerns about. First off, I recommend bulking up the capacitor on the reference pin to 10uF placed right at the reference input pin as a bulk charge. I am not sure but this should help with some of your noise issues on your output.
Layout is a secondary concern I have since it seems the analog outputs are noisy during SPI transmission. You may want to use an oscilloscope on your SPI lines and DOUT to see if you can see any coupling from either your /CS or SCLK into the analog output. See if during the clock edge transitions, you see noise spikes on the analog output showing coupling issues.
Looks like you have issues on the analog front and the digital side of things so best is to fix one side of things and then the other. My recommendation is to get a hold of one of our EVM boards for this DAC and fly wire into the SPI lines to get the code up and running. Once that is running, we can focus on the hardware and analog issues. Layout and passive components are key and is why we recommend following some of the reference design schematics shown in the DAC8718EVM UG and the data sheet.
Welcome to our forum! You posted quite a bit-o-detail about your project with the DAC8718! Is there any way you can let us take a look at you 'home brewed' layout? Gerber files or PDF of the layout perhaps?
Hi Tom, Hi Tony,
First of all I want to thank you very much for your attention and the time you spend on my problem(s).
Some information about myself: I'm a quite little experienced student of Biomedical Engineering who's doing his master thesis at the moment. I've made some digital, few analog and only one (very uncritical) mixed signal design untill now. So please don't be too hard to me when you see my layout which you see on figures 7 and 8.
For your information. I had one disign mistake. On the layout files it looks like the offset DACs are connected to ground. I corrected this manually, these pins are open now. Another modification is that I don't connect AGND and DGND using a jumper next to the analog power plug. Instead of this i installed a wire over the gap between AGND and DGND right next to C14 on the left hand side.
Keep in mind that this board is not made by a professional PCB manufacturer but with printing bottom and top layer on films and etching onto a double sided photoresist PCB. That explains why some descriptions are on the top layer instead of on top overlay.
Polarized capacitors are tantalum types, others ceramic.
For ease of reading of this thread for other people I decided to post images as well as one PDF (7750.Composite Drawing.pdf). Anyway, if you wish to get Gerber files, just tell me.
Figure 7: Top Layer of my DAC board. T1 to T9 are testpoints for accessing SPI signals and VMON.
Figure 8: Bottom Layer (top view, not mirrored) of my DAC board. Reference with buffer capacitor is placed on bottom side
@Tony: I don't undestand what measurements you want me to take. I think on the first three measurements one can see quite clearly that the output noise is caused by the SPI. So would you mind to tell me in a little bit more detail what I should do? I will take the neccessary measurements on monday.
The problem with the evaluation board is that the last time the university ordered parts for me, it took about 3 weeks until they actually placed the order. Time I didn't want to spend on solving this issue. Welcome to german bureaucracy. And 70USD is a lot of money for a student like me. Anyway, I will think about buying it by my own. Would you mind sending me the layout files of the evaluation board for getting an impression of how to do these things in the correct manner? Do you have access to my email address? Thanks a lot in advance.
i could manage to reduce noise amplitude by performing the following steps:
1. Making the oscilloscope probe sitting more tightly on the DACOUT pin and thus having (probably) better contact.
2. Soldering a 10µF tantalum capacitor close to the reference input pin of the DAC.
3. Removing the probes from the SPI lines.
4. Reducing DVDD and IOVDD from 3.3V to 2.7V.
Now it looks like shown in figure 9. Anyway, I hope it can be reduced futher with your help.
Figure 9: -16LSB step (approx. 1.8mV). Setup has changed to synchronous update mode using /LDAC with no effect on the noise.
sorry for being impatient, but will I get any further support? Any idea what could be the problem with my DAC8718? Maybe you can send me the layout files of the evaluation board. Thanks a lot in advance.
Attached are the Gerber files for the DAC8718EVM, the design was done using Protel 99, so we can provide you with the raw database as well if you can use that.
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