Hello,
I am currently working on board that will have 16 LMP90100 sampling J type thermo couple,
I have connected them all to FPGA ,all connected to same external Clock ,and I would like to synchronise them so that sampling will end approximatly in the same time
So that I will send 1 big packet to the CPU with all the 16 Readings without having latency in the Data.
(My concern is that if they wouldn't be synchronised they will open gap with time between Data outputs ,and I will need to wait to the last one before sending
The whole packet to the CPU)
I understand that there is a bit named "RESTART" that should synchronise the ADC,but my concern is that after each Synch I will need to wait to the Digital
Filter to "SETTLE" before data is valid so my throuput will be lower ,
My question is, can I after each Data reading from all the LMPs restart all ,by writing to the RESTART "bit" ?
Alternetly if I send to all "RESTART" once on system power up ,and all connected to same clock with same ODR all running background calibration ,will they open gap in outputs ready timing with time (By slightly different convertion time accomulated) ?
Or there is other way to sync them ?
Thanks for your help.
Hi Eyal,
First, you'll need to be sure your FPGA can drive 16 loads; you may need to insert one or two buffers for the SCLK and SDI lines and break up the LMP90100 into groups of four or eight. The same would be true for the CLK. I'll assume that you have 16 inputs on your FPGA for the SDO outputs from the LMP90100's. If you are careful with the layout and have good symetric placement (where there is minimal skew from one device to the next), using the RESET command and/or setting the RESTART bit should give you synchronized results. I'm not sure that anyone from our side has tried this, so we'll let you know if there are any 'tips or tricks' for getting this to work
Regards,
Tom
Hi Tom,
Thanks for the reply ,I am not sure I explained my self clear enough.
I am going to connect seperate SPI bus between the FPGA and each LMP90100 so no concern about loading ...etc .
My concern is :if I will wait for all 16 chs to finish the sampling and than each time send Restart command to sync all the ADCs in order to verify that time between ADCs samples will
not get accomulated with time ,will I need to wait to the Digital filter indise the ADC to "settle" or I will get valid data at the end of the next convertion ?
Example: if ADC convertion time of ch1 is x and for channel 2 is y and x<y than If I will not send sync command after each convertion, I will get accomulated time difference between end of convertion of Ch1 and Ch2 which will be equal to N*(y-x) ,which is N is number of convertions from last Sync command.
This phenomena will make the time to gether all the 16 ch values in packet , expanding up with time which is bad for my system.
Thanks.
Yes, You can restart conversion by writing to RESTART bit.
LMP90100 outputs only fully settled values. i.e when you restart and read data on DRDYB assertion you will read a fully settled output.
Regards,Murali
Murali Srinivasa Hi Eyal, Yes, You can restart conversion by writing to RESTART bit. LMP90100 outputs only fully settled values. i.e when you restart and read data on DRDYB assertion you will read a fully settled output. Regards,Murali
Thanks for the relpy Murali,
My concern is that after the RESTART command the Digital filter is flushed and Settle time of the filter will take more than 1 convertion Cycle
like usualy in Sigma Delta ADCs when Step input is injected .
So the question is do the Digital filter is flushed after Restart command and how many Convertion cycles it takes to settle ?
Anyone can help ?
Regards
Hi Eyal,After restart command is sent, digital filter will be flushed. But LMP90100 has Incremental Sig-del ADC, hence there is no difference between the output datarate and the time for output of the first settled output. i.e if 'x sec' is the time taken for the first settlet output, then the subsequient outputs will be spaced by 'x sec' (data rate= 1/x ).Unlike other converters where there is an intial settling time of ' y sec' and subsequent data output at 'x sec' ( y sec settling time + 1/x is data rate).