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Precision Data Converters
Precision Data Converters Forum
DAC8564 intermittent issues
I use the Dac 8564 in two products.
Recently , i have discovered two issues ? , which i think are related somehow.
The dac, sometimes refuses to acknowledge spi commands and acts as if it is not selected. ( this may have been fixed by changing decoupling cap to 10uf from 1uf)
this happens when the device is cold but seems to stop misbehving when warmer, although i am hoping that the above 10uf cap will be the fix for this.
the more serious issue
The dac ref changes from 2.5V to a different voltage i.e 3.8V, 4.1V even though no parts are connected except for 1uf cap
This happens whenever a ramp or 100 % Fs SQ wave is generated by a SW test
This does not happen when zeros are loaded or a small amplitude sq wave is loaded ( 1/4 to 3/4 scale @1Khz, 20ksample/sec update)
When the int ref is set to "off" the ref pin goes to zero
Pwr is AVdd=5V from buffered ref, Vddio=3.3V pin 5,6 connected to Agnd
Why does to ref generate these peculiar voltages ? ( This seems to be releated to glitches generated by large output signal transitions, as it doesnt happen when constant values are output) The dac seems to work better when a sine wave is output but the problem still happens
I have tried,
100uf caps on psu pins
any other suggestions ?
A couple comments -
It sounds like you may have an oscillating reference. Double check with an oscilloscope that you do not have an oscillating internal reference due to the size of the capacitor that you have on the Vref line. 100uF is very high and the internal buffer for the Vref out cannot drive that causing your reference to be unstable. You will want a 1-4uF capacitor on the Vrefout line.
Secondly, make sure that all of your digital pins are low at power up (especially the /SYNC pin). We have a statement in the datasheet that no pin should be brought high until the power is applied to the device. Some customers have had similar issues which came down to the digital I/O lines high prior to power applied to the device.
Thanks for your reply
I tried your suggestions with no joy but today have finally fixed it.
The problem turned out to be SOFTWARE !
I have two Dacs on my cct and one of the dac had a sync signal which was "ORed" with the other one.
Why the Dac Ref goes crazy when this happens is unkown. I expected the sync terminating a cycle early would be ignored but this does not seem to be the case. Anyhow a fix is a fix
thanks for yr help
I intend to use multiple DAC8564 in an application with a 3wire SPI Interface similar to 68HC11. The DAC has 2-bit hardwired addressing scheme, but since I want to use five of them, I am examining the case to implement the interface using the !ENABLE signal to individually address each one of them. The datasheet reports that this can be done with the restriction that SCLK, !SYNC, and DIN signals must be at some logic level (not floating).
These signals will be routed as a bus structure, and there is the possibility in some point while transferring data to one of them (actually after one complete transfer), the MOSI signal from the controller, to be in Hi-Z state (virtually open circuit).
Will this cause any problems in the internal SPI state machine of the disabled DACs??
Thank you in advance.
The DAC8568 is the eight channel version of the DAC8564 and may be a better fit if you need more channels. Have you considered looking at it?
If I understand your question correctly, you are asking if you can use the ENABLE pin as, more or less, a /CS to help control talking to more than four DAC8564s. That should be fine as long as the three SPI lines are not floating. The interface is a little different than a standard SPI interface where the /CS functionality is broken up into two pins: /SYNC, and /ENABLE. /SYNC is used for updating the data word or aborting a command while /ENABLE is used to physically connect and disconnect the SPI bus to the digital block of the chip.
If you are concerned with the controller going into a state where the DIN to the DACs will be floating, you can try using a very weak pull down resistor on the line (100k). In our experience, it is never a good idea to have an input pin floating, whether it is analog or digital. You always want to have the pin in a known state to avoid having a device enter an "unknown state."
Thank you very much for your reply and recommendation.
I have already started examining the case with DAC8568, as this device does not have !ENABLE and hardwired address signals. I will make use of the separate CS signals of the microcontroller SPI block, to drive the !SYNC signals. I will also use the weak pull down resistor on each DIN line, because it is somewhat uncertain weather the MOSI line of the micro will or wont be in a Hi-Z state.
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