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ADS1298 SCLK inconsistency or misunderstanding?
Hi, I'm sorry. I'm trying to understand real rates, and times when I choose some data rate and the SPI speed in my system.
page 31 on ADS1298 stays that tsclk < tdr / 216 (for 24, 8 channels). That's mean that at 500SPS tsclk < 9.25useg = 110Khz (aprox)
by the other hand
page 15 stays that min tsclk = 50nseg. By extracting 216bits by SPI channel, this means 50 * 216 = 10.8useg
If I don't make a mistake, page 31 stays a speed lower than the minimum speed specified in page 15 for the SPI port ???.
May be, my mistake is not understand what means data rate at all. Is it the speed to obtain one single bit converted or the speed to obtain a group of 24bits converted (the whole analog signal at a single instant) ?
Please, I will appreciate if you can clarify my doubt.
Best regards, Esteban
Page 15 is describing the minimum SCLK period (50 or 66.6ns) which is actually the maximum SCLK speed the ADS1298 can tolerate. Page 31 is describing the minimum SCLK speed you can use to get all data out of the ADS1298. The 10.8us is equal to taking 216 bits (8 channels plus the status byte) with a 20MHz SCLK. The inverse of 10.8us is 92.6kSPS, which is nearly 3 times the maximum data rate the ADS1298 can support.
The data rate is the time period between DRDY pulses. At the maximum speed or 32000SPS, you would see a DRDY pulse every 31.25us. Your SCLK has to be fast enough to get all the data out of the device before another DRDY pulse comes along.
Thanks Tom, I think I get it.
So, you said: "The data rate is the time period between DRDY pulses. At the maximum speed or 32000SPS, you would see a DRDY pulse every 31.25us".
Because in the ADS1298 the eight Delta-Sigma ADC are in paralell mode, that means I've the eight 24bits-channels with valid data ready to be read by the SPI port every 31.25us. So, I must to use a SCLK faster than 31.25us to read them all without missing data. If I understood well right, the minimun tSCLK must be 31.25us / 216 = 145ns which is equal to use a fSCLK faster than 6.912Mhz, isn't it ?
berst regards, Esteban
Yes - I believe you've got it! I think you may have forgotten to subtract the 4*tCLK though; the MIN SCLK speed is just over 7MHz to get all data at 32000sps.
Yes, Tom, I think I got it! Thanks at all. If you don't mind I'll appreciate to continuing asking to you about ADS1298 on this topic.
best regards, Esteban
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