Working currently with 4 ADS1282 devices, I have troubles synchronizing the ADC devices together. To make it as clear as possible, here is the set-up used:
1) Power on switching
2) SDATAC command
3) Write/read registers
4) RDATAC command
5) Taking Sync pin low
6) Taking Sync pin high (sync event)All ADCs have the same configuration (Continuous Sync mode, 500SPS, other parameters as defaults).
The clock, sync and reset signals are shared for a 4 ADCs. All 4 devices get the SYNC signal at the same time.
However, after 63 samples re-synchronization cycles, the drdy_n signals are not going down at the same time for the 4 ADCs, hence a small offset in the data sampling. I am then wondering if I did something wrong while configuring the ADC, or what could be the source of such a sync mismatch.
Thank for any idea you can provide.
If you are sharing the master clock among the 4 devices, and the SYNC pin signal is also shared across the devices, the SYNC should work properly, provided the devices are in close proximity to each other and they are receiving the same synchronized clock and SYNC signal without delays.
In continuous-sync mode a single SYNC event could be used or a continuous clock with a period equal to integer multiples of the data rate can be applied. Page 24 of the datasheet describes that in Continuous-sync mode that when the rising edge of the sync pulse is applied, DRDY continuous to toggle unaffected but the DOUT output is held low until data are ready, 63 DRDY periods later.
How big is the offset between the different DRDY signals and are the DOUT signals toggling high at the same time when the new data is ready ? Are the devices in thesame PCB board? If the devices are in the same PCB board, how far away are they place from each other?
What kind of oscillator is used for a clock source? How much time is allowed for the internal oscillator and circuitry to stabilize after power up? If you have an schematic and board layout available we will be happy to review it.
Thank you for the answer. About the offset between the DRDY signals, it is too big for being just a timing mismatch with the clock signal, as we are at least talking about 50 clock cycles... Also, all 4 ADCs are on the same board with very short and pretty much equal paths to and from the driving FPGA.
The oscillator used is a classical 16MHz crystal oscillator, divided in the FPGA to a 4MHz clock, outputted then to the ADC devices. The power-up time is one second, and then registers are correctly written and read after that time. Sync event occurs only after these commands.
Board layout and schematics are unfortunately confidential but I think the above description sums them up quite well.
If the devices are sharing the same SYNC connection, I would expect the devices to synchronize.
If possible, can you please post a scope shot of the DRDY and SYNC signals? The SYNC pulse needs to be at least 2 tclk cycles long; a suggestion may be to set the Sync pulse width to 4 tclks (conservative) to ensure the SYNC pulse is asserted without timing issues. If the device is set up in Pulse-Sync mode with the CONFIG0 BIT=0 (default); are you able to synchronize the devices?
Thank you and Best Regards,
I would for sure expect the same thing. But so far, it sounds very disturbing.
I managed a couple of time to get them synchronized, simply by compiling and place & routing again the same FPGA code ( the FPGA handles the ADC devices). Also sometimes, the ADC devices get synchronized two by two ( ADC0 and ADC1 are synchronized together and ADC2 and ADC3 are synchronized together).
The SYNC signal is held low around half a second, before being set up again. I suppose the ADC to synchronize on the rising edge of the sync signal. Is the fact the sync low state is quite long can be a problem ?
Also, I tried to set the default Pulse-sync mode and the same behavior occurs: the ADC devices do not synchronize.
Any idea ?
The ADS1282 device is widely used by customers in applications that require to synchronize the devices; and one of our bench systems has (4) ADS1282's where the devices are synchronized.
- Are the Sync pins of the (4) ADS1282's physically connected together to the same FPGA output pin? One problem I have seen in the past was in an application where each device was connected to a different GPIO pin and the signals generated by the FPGA were not in perfect Sync. If the devices are not connected to the same output pin, please physically connect them or short them together and experiment first with the Pulse-Sync mode. Please provide oscilloscope plots of the Sync signals of the four devices and the respective DRDY signals
In the Continuous-Sync mode when a single Sync pulse is provided, the device will stop and start the conversion on the rising edge of the pulse. When a Sync clock signal is provided, the device will synchronize on the first pulse applied and afterwards under the condition where the SYNC period is not an integer multiple of the data rate. The datasheet does not specify a maximum period (tsync) for the timing for the sync clock; therefore, I don't expect the SYNC being in a low state for a long time to be an issue.
Yes, the Sync pins of the 4 ADS1282's are physically connected together to the same FPGA output pin.
The sync signal has the following pattern: Up from the power up to time T (around 1second from power up). Then down for half a second. Finally up again until the end.
I have troubles understanding the figure 52 in the datasheet in case of a continuous sync mode. Why is the sync pin rising, falling and then rising again ?
Can you please explain me which pattern is asserted on the common SYNC pin in your bench system for 4 ADS1282 for a continuous sync mode ? Can you provide a clearer picture than the one in the datasheet ?
When the SYNC pin is asserted high, the resynchronization occurs on the next rising master CLK edge after the SYNC rising edge. The datasheet figure 52 shows a SYNC signal rising, falling and then rising again in order to show the timing requirements for SYNC pulse minimum width high and low. A minimum of 2 tclk's width or about 488ns is required. It is only necessary to provide a single rising edge of the SYNC pin in order for the devices to synchronize.
I performed a few experiments, synchronizing two ADS1282 devices. I used the device with the default settings in Pulse Sync Mode and drove them with the same function generator source of 4.096MHz master clock and pulsed the SYNC pins with different waveforms. The SYNC pins where also connected together to the same function generator...
-- On the first experiment, I drove the SYNC pins with a single pulse, starting with the SYNC pin low and applying a single pulse of minimum 488ns width; the DRDY device signals synchronized without issues.
-- On the second experiment, I started with the SYNC pin high after power up, then toggled the SYNC low for about half a second and toggled the SYNC pins high again. The device synchronized on the rising edge of SYNC without issues.
During the experiments, I noticed that the rising edge slew rate of the SYNC pulse must be sharp. If the SYNC signal rising edge slew rate was purposely set too slow compared to the master clock, the DRDY signals of the devices could be off by a few clock cycles. Provided that the SYNC rising edge had a slew rate comparable or similar to the 4.096 MHz master clock; no issues occurred.
Please find attached some of the oscilloscope plots of the experiments.
--- Please provide oscilloscope shots of the shared SYNC signal, Master clock and the respective DRDY signals in order to check the timing and slew rate of the SYNC signals; for simplicity, please start with the device set up on the PULSE-SYNC mode.
Thank you and Regards,
Thank you very much for trying all this.
I did the same on my side, but wasn't able to print out the oscilloscope plots. I will report it as text below:
Sync signal: low state 0V, high state 1.8V. Rising time ~2ns
Drdy_n signal: 2 signals could not be seen together on the same plot, implying a synchronization mismatch with a big gap. However, their voltage parameters are the same (0-1.8V, 2ns rising edge) as the sync signal.
We tried synchronization with the SYNC SPI command and it works well. But I was wondering one thing: In Continuous-Sync Mode, when applying a rising edge on the SYNC pin, it should comes after around 63 samples which are "0"s. However, it is not mentioned in the datasheet if these "0"s should appear when using the SYNC SPI command (still in the continuous-sync mode). Actually, I don't get any "0", but instead no samples for the same period (63 samples time). Can you confirm that it is right ?
We have now a working workaround, using the software way (SPI command), but the fact we are not able to communicate with the Sync pin does not look good, and can hide something else, so I would like to investigate a bit more on that point.
Also, I checked the main clock, which is also from 0 to 1.8V, running at 4.096MHz. the rising/falling time is 20ns.
Do these values seem correct ?
After the SYNC command is issued, the DOUT should go low for 63 samples. I tested using both the CONTINUOUS-SYNC mode and the PULSE-SYNC mode. On the Continuous SYNC-MODE this will happen when the SYNC command or signal is first applied or it will occur if the SYNC clock signal or SYNC event is not an integer multiple of the sampling rate.
When you mention the DRDY_N signal being at the high state 1.8V, does this you mean the amplitude toggles up to 1.8V? or the parameter threshold is 1.8V on the program? The DRDY signals should toggle up to the digital supply DVDD. The device can work with a supply as low as 1.65V. I experimented with a 1.8V DVDD supply and the device worked well providing DRDY pulses to 1.8V and the devices synchronized.
The rising times you have provided are very fast (2ns); I don't see this as a problem. The rising times of my set up are slower in the order of ~10ns.
And about the DRDY_N signal, it is the amplitude which toggles between 0 to 1.8V. The digital power supply DVDD is 1.8V for the 4 ADS1282.
I think we found an interesting thing today: We measured the time in between the Sync signal rising edge and the main clock rising edge. and we found something very close to 10ns, which is the T(hold) and T(setup) time of the ADS1282 chip.
We then moved the Sync signal rising edge towards the main clock falling edge and it seems now to work. It is still under investigation, but it may be a lead.
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