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ADS1259 DRDY Output

This question is answered
Justin Forrester
Posted by Justin Forrester
on Jun 12 2012 12:07 PM
Expert1015 points

Hello,

I am having an issue where I am getting duplictate/inserted data points when sampling from the ADS1259.  As a test I set up a GPIO line on my processor to output high when two sequential readings are equal and low when they are different.  I then used that as a trigger on my scope to see what the DRDY line is doing when a duplicate sample is detected.  As you can see below (top signal is the GPIO line, bottom is DRDY), sometimes DRDY does not return high when clocking out data.  Since my code initiates sampling when it detects that DRDY is low, I am obtaining the same data point twice.  Do you have any idea what may be causing this issue and how I may resolve it?

Thanks,

Justin

SPI ADS1259 SSI
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  • Luis Chioye
    Posted by Luis Chioye
    on Jun 12 2012 13:13 PM
    Verified Answer
    Verified by Bob Benjamin
    Genius17435 points

    Hello Justin,

    When reading conversion results from the ADS1259 on the RDATAC mode, the user must monitor the Falling edge of the DRDY signal.  Typically the processor would be set up in a routine with an interrupt that detects the falling-edge of DRDY to read the conversion data.  When using the device on RDATAC mode, the data read operation must be complete 20flck cycles before of the next DRDY cycles; before the update of the output register with new conversion results occur.  The same conversion data could be read again by continuing to shift data;  Notice, it is not sufficient to detect when DRDY is low, but to detect the falling edge of DRDY to read the data.

    What kind of signal is being fed to the ADS1259?

    Best Regards,

    Luis

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  • Justin Forrester
    Posted by Justin Forrester
    on Jun 12 2012 15:08 PM
    Expert1015 points

    Luis,

    For the specific test I was running when I generated that screen shot, the ADS1259 was being given a 1KHz 20mVpp sine wave offset +15mV.

    I will likely implement an interrupt routine for this purpose, however, I that still leaves the question of why the DRDY line is behaving as it is.  According to the figure you attached, note 1 specifies that DRDY should return high on the first falling edge of SCLK. However, in some instances DRDY does not return high until at least the start of the second full read operation (on the 25th falling edge).

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  • Bob Benjamin
    Posted by Bob Benjamin
    on Aug 03 2012 11:25 AM
    Mastermind34195 points

    Justin,

    Were you able to resolve your issue? Usually these types of issues are related to timing.

    Best regards,

    Bob B

    ADS1259
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