Regarding the 3 wire CS mode with busy mode. In the data sheet (Pg 14-15) I read that on the 17th falling edge of the SCLK the SDO goes tri-state. It also states that a minimum of 16 clocks are required and you may use the Conversion start to bring it back into tri-state. As for the data transfer, It states "The device outputs the MSB of data on the first falling edge of SCLK after the conversion is over and continues to output the next lower data bits on every subsequent falling edge of SCLK." Does this mean that the data is transfered on the first 16 falling edges and the 17th is the tri-state mechanism or is the first falling edge a trigger to get the data ready and the data is transfered on falling edges 2-17. The diagram which follows Figure 48 clearly shows the data being clocked in on falling edges 2-17. I am slightly confused.
Thanks in advance for any help.
Figure 48 is correct. The first falling edge is a trigger and edges 2-17 are used to output the data. SDO goes to three state after the 17th falling edge of SCLK or CONVST high, whichever occurs first.
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