ssory for full qustion, I'm not familiar with sigma-delta and differential-input ADC.
(Schematic on page 43 of ADS1258.pdf (SBAS297E–JUNE 2005–REVISED OCTOBER 2007) figure 67)
question: If ADCINP < ADCINN what code will I get? For example, ADCINP-ADCINN = -0.5(RefP-RefN) I will get 1xxxxxx code, and if ADCINP-ADCINN = 0.5(RefP-RefN) I will get 0xxxxx code?
thanks to all, I found reply to my question on page 24.
Next question: If I connect -2.5V analog supply to RefN pin, will I have problems with noise in ADC results for unstable -2.5V. I guess -2.5V will be anstable due tu pulsed supply current of ADC.
Yes, if your reference isn't stable, then you will see that reflected in the output code.
If the problem is noise coming from the power supply itself, using a simple low-dropout regulator often gives good results along with adequate filtering of the reference input.
Your question was about if the ADC itself would disturb the supply - perhaps, but with proper bypassing and layout this should not be a problem.
Remember that the reference the ADC sees is the difference between VREFP and VREFN, so if VREFN goes up, and so does VREFP, then there will be no problem. This is why Figure 67 in the datasheet is done as it is - note that the REF3125 is referenced to the -2.5V.
(page 61 of ADS1258: The reference inputs should be driven by a low-impedance source. For rated performance, the reference should have 3uVRMS broadband noise.For references with higher noise, external filtering may be necessary)
1) In most applications and evaluation boards we can see the reference buffered with Op.Amp. Is it necessary? Can I use a ADR444BRZ Reference with 10 uF (or 220 uF) capacitor without Op. Amp.?
Will ADR444BRZ be stable with 220uF capasitor? (cant find such frase in ADR444BRZ pdf)
3) If i want to have adc error 0.1% and referense 5V, I can have the amplitude of reference noise 5/0.001=5mV? (If the acuracy of reference = 0%, and ADC has no DNL and INL).
One more question: (page 17 ADS1258.pdf) Is the Modulator input sampling Rate = fCLK/2 ? So, at 16 MHz clk, I need to reduce adc input noise in 8Mhz, 16Mhz, 24Mhz,32 Mhz...
Buffering the reference is usually necessary on this device. The modulator runs nominally at 8MHz, which means that reference is pulling current every 125ns. A good size bulk capacitance can help, but the charge on it must be replenished quickly, so a fast op amp with low output impedance is necessary.
I can't tell you much about the ADR444BRZ, you'll need to ask the manufacturer about that. Looking at the output impedance curve of that device's data sheet, I would say it probably would be quite high by the time you get to 8MHz, and so wouldn't be suitable by itself.
Given the conditions you list (not considering INL/DNL and initial ref accuracy), then yes, your reference calculation is correct.
And yes, you are correct - the modulator would run at 8Mhz with a 16MHz clock, so you must prevent coupling noise it at 8MHz - usually a simple RC filter works fine, and make sure your layout doesn't do something like run the clock line under the analog input pins (I've seen it happen...)
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