Component : ADS1217
Datasheet : SBAS260C
It's explain on the ADS1217's datasheet (p17) : that when the decimation
register DEC0 & DEC1are set by default (1920) with a 2.4576MHz crystal, the
data rate frequency is 10Hz so the /DRDY output should be at the same
I check that with the following equation(p24) :
Decimation Ratio = Fosc/(mfactor*Fdata)
There is my registers
SETUP(00h) = 00001110
IDAC1(03h) = 11010000
IDAC2(04h) = 00010100
ODAC(05h) = 00000000
DEC0(08h) = 10000000
The others register are set by a SELFCAL command.
The /DRDY output frequency
is 9.4Hz instead of 10Hz...
Does this shift is explain
on any datasheet? If yes which one?
this error is the same with all the components?
Thanks you by advance for all yours support.
Have you checked that the fOSC frequency is really 2.4576MHz? Could it be that your crystal is being "pulled" to a lower frequency by inappropriate load caps? With 2.4576MHz exactly going in, you should get 10Hz out on /DRDY with the register settings you have.
In fact the /DRDY clock was ok but when I select an other channel I miss two falling edge.
That why i thought that there was a bad frequency on /DRDY.
But i still don't understand why selecting channel change the DRDY clock?...
Well, it took some digging, but there is an explanation: on the ADS1217, unlike its cousins the ADS1216 and ADS1218, the DRDY is suppressed until the filter fully settles. So since you're using the sinc3 filter setting, whenever you change channels the part holds off sending DRDY until the third conversion after the channel change completes. That's why you're missing two DRDYs when you change channels.
Allright! Thank you for your help.
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