• Resolved

ADS8028: ADS8028 Min CS high time required in Repeat mode

Part Number: ADS8028

Hi, Experts:

My customer is using ADS8028 in repeat mode to sample the analog signal.

While we found that if we make the CS high time at the level of few hundreds of ns between each SPI cycle, the ADC sampled data will show errors, which means the ADC codes returned cannot match the analog signal well.

If we increase the CS hign time between each SPI cycle from few hundereds of ns to several us, we don't see this ADC error codes returned.

According to our datasheet, the min CS high time is 6ns as below

I take a measurement of our SPI timing on TI EVM in repeat mode:

The overall timing consists of: the 1st SPI cycle to write the control register, the 2nd SPI  cycle to wait for conversion complete, the 3rd SPI cycle and following cycles to read back the retured ADC code continuously as below:

The CS high time between 1st SPI cycle and 2nd SPI cycle is 2us as below:

The CS high time between 2nd SPI cycle and 3rd SPI cycle is very long, ~26us as below:

The CS high time between following SPI cycles is around 150ns:

Can I double check with you if there any special requirements for the CS high time between each SPI cycles in Repeat mode?

Thank you for your help in advance!